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74VHC164 fiches techniques PDF

Fairchild Semiconductor - 8-Bit Serial-In/ Parallel-Out Shift Register

Numéro de référence 74VHC164
Description 8-Bit Serial-In/ Parallel-Out Shift Register
Fabricant Fairchild Semiconductor 
Logo Fairchild Semiconductor 





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74VHC164 fiche technique
August 1993
Revised April 1999
74VHC164
8-Bit Serial-In, Parallel-Out Shift Register
General Description
The VHC164 is an advanced high-speed CMOS device
fabricated with silicon gate CMOS technology. It achieves
the high-speed operation similar to equivalent Bipolar
Schottky TTL while maintaining the CMOS low power dissi-
pation. The VHC164 is a high-speed 8-Bit Serial-In/Paral-
lel-Out Shift Register. Serial data is entered through a 2-
input AND gate synchronous with the LOW-to-HIGH transi-
tion of the clock. The device features an asynchronous
Master Reset which clears the register, setting all outputs
LOW independent of the clock. An input protection circuit
insures that 0V to 7V can be applied to the input pins with-
out regard to the supply voltage. This device can be used
to interface 5V to 3V systems and two supply systems such
as battery backup. This circuit prevents device destruction
due to mismatched supply and input voltages.
Features
s High Speed: fMAX = 175 MHz at VCC = 5V
s Low power dissipation: ICC = 4 µA (max) at TA = 25°C
s High noise immunity: VNIH = VNIL = 28% VCC (min)
s Power down protection provided on all inputs
s Low noise: VOLP = 0.8V (max)
s Pin and function compatible with 74HC164
Ordering Code:
Order Number Package Number
Package Description
74VHC164M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
74VHC164SJ
M14D
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC164MTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC164N
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names
Description
A, B Data Inputs
CP Clock Pulse Input (Active Rising Edge)
MR Master Reset Input (Active LOW)
Q0–Q7
Outputs
© 1999 Fairchild Semiconductor Corporation DS011636.prf
www.fairchildsemi.com

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