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PDF 74VCXH16240 Data sheet ( Hoja de datos )
| Número de pieza | 74VCXH16240 | |
| Descripción | Low Voltage 16-Bit Inverting Buffer/Line Driver with Bushold | |
| Fabricantes | Fairchild Semiconductor | |
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December 1999
Revised March 2000
74VCXH16240
Low Voltage 16-Bit Inverting Buffer/Line Driver
with Bushold
General Description
The VCXH16240 contains sixteen inverting buffers with 3-
STATE outputs to be employed as a memory and address
driver, clock driver, or bus oriented transmitter/receiver.
The device is nibble (4-bit) controlled. Each nibble has sep-
arate 3-STATE control inputs which can be shorted
together for full 16-bit operation.
The VCXH16240 data inputs include active bushold cir-
cuitry, eliminating the need for external pull-up resistors to
hold unused or floating inputs at a valid logic level.
The 74VCXH16240 is designed for low voltage (1.65V to
3.6V) VCC applications with output capability up to 3.6V.
The 74VCXH16240 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
s 1.65V–3.6V VCC supply operation
s 3.6V tolerant control inputs and outputs
s Bushold on data inputs eliminates the need for external
pull-up/pull-down resistors
s tPD
2.5 ns max for 3.0V to 3.6V VCC
3.0 ns max for 2.3V to 2.7V VCC
6.0 ns max for 1.65V to 1.95V VCC
s Static Drive (IOH/IOL)
±24 mA @ 3.0V VCC
±18 mA @ 2.3V VCC
±6 mA @ 1.65V VCC
s Uses patented noise/EMI reduction circuitry
s Latch-up performance exceeds 300 mA
s ESD performance:
Human body model > 2000V
Machine model > 200V
Ordering Code:
Order Number
74VCXH16240MTD
Package
Number
MTD48
Package Descriptions
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
OEn
I0–I15
O0–O15
Description
Output Enable Input (Active LOW)
Bushold Inputs
Outputs
© 2000 Fairchild Semiconductor Corporation DS500232
www.fairchildsemi.com
1 page  
AC Electrical Characteristics (Note 13)
TA = −40°C to +85°C, CL = 30 pF, RL = 500Ω
Symbol
Parameter
VCC = 3.3V ± 0.3V
VCC = 2.5V ± 0.2V
VCC = 1.8V ± 0.15V
Units
Min Max Min Max Min Max
tPHL, tPLH Prop Delay
0.8 2.5 1.0 3.0 1.5 6.0 ns
tPZL, tPZH Output Enable Time
0.8 3.5 1.0 4.1 1.5 8.2 ns
tPLZ, tPHZ Output Disable Time
0.8 3.5 1.0 3.8 1.5 6.8 ns
tOSHL
tOSLH
Output to Output Skew
(Note 14)
0.5 0.5 0.75 ns
Note 13: For CL = 50PF, add approximately 300 ps to the AC maximum specification.
Note 14: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Dynamic Switching Characteristics
Symbol
Parameter
VOLP
Quiet Output Dynamic Peak VOL
VOLV
Quiet Output Dynamic Valley VOL
VOHV
Quiet Output Dynamic Valley VOH
Conditions
CL = 30 pF, VIH = VCC, VIL = 0V
CL = 30 pF, VIH = VCC, VIL = 0V
CL = 30 pF, VIH = VCC, VIL = 0V
VCC TA = +25°C Units
(V) Typical
1.8 0.25
2.5 0.6
V
3.3 0.8
1.8 −0.25
2.5 −0.6
V
3.3 −0.8
1.8 1.5
2.5 1.9
V
3.3 2.2
Capacitance
Symbol
Parameter
CIN
COUT
CPD
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
Conditions
TA = +25°C
Typical
VCC = 1.8, 2.5V or 3.3V, VI = 0V or VCC
VI = 0V or VCC, VCC = 1.8V, 2.5V or 3.3V
VI = 0V or VCC, f = 10 MHz, VCC = 1.8V, 2.5V or 3.3V
6
7
20
Units
pF
pF
pF
5 www.fairchildsemi.com
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet 74VCXH16240.PDF ] | |
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