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PDF 74VCX16601 Data sheet ( Hoja de datos )
| Número de pieza | 74VCX16601 | |
| Descripción | Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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March 1998
Revised April 1999
74VCX16601
Low Voltage 18-Bit Universal Bus Transceivers with 3.6V
Tolerant Inputs and Outputs
General Description
Features
The VCX16601 is an 18-bit universal bus transceiver which
combines D-type latches and D-type flip-flops to allow data
flow in transparent, latched, and clocked modes.
Data flow in each direction is controlled by output-enable
(OEAB and OEBA), latch-enable (LEAB and LEBA), and
s 1.65V–3.6V VCC supply operation
s 3.6V tolerant inputs and outputs
s tPD (A to B, B to A)
2.9 ns max for 3.0V to 3.6V VCC
clock (CLKAB and CLKBA) inputs. The clock can be con-
trolled by the clock-enable (CLKENAB and CLKENBA)
inputs. For A-to-B data flow, the device operates in the
3.5 ns max for 2.3V to 2.7V VCC
7.0 ns max for 1.65V 1.95V VCC
transparent mode when LEAB is HIGH. When LEAB is s Power-down high impedance inputs and outputs
LOW, the A data is latched if CLKAB is held at a HIGH-to- s Supports live insertion/withdrawal (Note 1)
LOW logic level. If LEAB is LOW, the A bus data is stored
in the latch/flip-flop on the LOW-to-HIGH transition of
CLKAB. When OEAB is LOW, the outputs are active. When
s Static Drive (IOH/IOL)
±24 mA @ 3.0V VCC
OEAB is HIGH, the outputs are in the high-impedance
state.
Data flow for B to A is similar to that of A to B but uses
OEBA, LEBA, CLKBA and CLKENBA.
±18 mA @ 2.3V VCC
±6 mA @ 1.65V VCC
s Uses patented noise/EMI reduction circuitry
The VCX16601 is designed for low voltage (1.65V to 3.6V) s Latchup performance exceeds 300 mA
VCC applications with I/O capability up to 3.6V.
s ESD performance:
www.DataSheet4U.com
The VCX16601 is fabricated with an advanced CMOS
Human body model > 2000V
technology to achieve high speed operation while maintain-
Machine model >200V
ing low CMOS power dissipation.
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Order Number Package Number
Package Description
74VCX16601MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pin Descriptions
Pin Names
Description
OEAB, OEBA
Output Enable Inputs (Active LOW)
LEAB, LEBA
Latch Enable Inputs
CLKAB, CLKBA
Clock Inputs
CLKENAB, CLKENBA Clock Enable Inputs
A1–A18
B1–B18
Side A Inputs or 3-STATE Outputs
Side B Inputs or 3-STATE Outputs
© 1999 Fairchild Semiconductor Corporation DS500126.prf
www.fairchildsemi.com
1 page  
AC Electrical Characteristics (Note 11)
TA = −40°C to +85°C, CL = 30 pF, RL = 500Ω
Symbol
Parameter
VCC = 3.3V ± 0.3V
VCC = 2.5 ± 0.2V
VCC = 1.8V ± 0.15V
Units
Min Max Min Max Min Max
fMAX
Maximum Clock Frequency
250
200
100 MHz
tPHL Propagation Delay
0.8 2.9 1.0 3.5 1.5 7.0 ns
tPLH Bus to Bus
tPHL Propagation Delay
0.8 3.5 1.0 4.4 1.5 8.8 ns
tPLH Clock to Bus
tPHL Propagation Delay
0.8 3.5 1.0 4.4 1.5 8.8 ns
tPLH LE to Bus
tPZL Output Enable Time
0.8 3.8 1.0 4.9 1.5 9.8 ns
tPZH
tPLZ Output Disable Time
0.8 3.7 1.0 4.2 1.5 7.6 ns
tPHZ
tS Setup Time
1.5 1.5 2.5
ns
tH Hold Time
1.0 1.0 1.0
ns
tW Pulse Width
1.5 1.5 4.0 ns
tOSHL
Output to Output
0.5 0.5 0.75 ns
tOSLH
Skew (Note 12)
Note 11: For CL = 50pF, add approximately 300ps to the AC maximum specification.
Note 12: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Dynamic Switching Characteristics
Symbol
Parameter
VOLP
VOLV
VOHV
Quiet Output Dynamic
Peak VOL
Quiet Output Dynamic
Valley VOL
Quiet Output Dynamic
Valley VOH
Conditions
CL = 30 pF, VIH = VCC, VIL = 0V
CL = 30 pF, VIH = VCC, VIL = 0V
CL = 30 pF, VIH = VCC, VIL = 0V
VCC
TA = +25°C
Units
(V) Typical
1.8 0.25
2.5 0.6
3.3 0.8
V
1.8 −0.25
2.5 −0.6
3.3 −0.8
V
1.8 1.5
2.5 1.9
3.3 2.2
V
Capacitance
Symbol
Parameter
CIN Input Capacitance
CI/O Output Capacitance
CPD Power Dissipation Capacitance
Conditions
VI = 0V or VCC
VCC = 1.8V, 2.5V, or 3.3V
VI = 0V or VCC,
VCC = 1.8V, 2.5V or 3.3V
VI = 0V or VCC, f = 10 MHz
VCC = 1.8V, 2.5V or 3.3V
TA = +25°C
6
7
Units
pF
pF
20 pF
5 www.fairchildsemi.com
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| PDF Descargar | [ Datasheet 74VCX16601.PDF ] | |
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