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PDF 74LVXC4245QSC Data sheet ( Hoja de datos )
| Número de pieza | 74LVXC4245QSC | |
| Descripción | 8-Bit Dual Supply Configurable Voltage Interface Transceiver with 3-STATE Outputs | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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February 1994
Revised July 1999
74LVXC4245
8-Bit Dual Supply Configurable Voltage Interface
Transceiver with 3-STATE Outputs
General Description
The LVXC4245 is a 24-pin dual-supply, 8-bit configurable
voltage interface transceiver suited for PCMCIA and other
real time configurable I/O applications. The VCCA pin
accepts a 5V supply level. The “A” Port is a dedicated 5V
port. The VCCB pin accepts a 3V-to-5V supply level. The
“B” Port is configured to track the VCCB supply level
respectively. A 5V level on the VCC pin will configure the
I/O pins at a 5V level and a 3V VCC will configure the I/O
pins at a 3V level. This device will allow the VCCB voltage
source pin and I/O pins on the “B” Port to float when OE is
HIGH. This feature is necessary to buffer data to and from
a PCMCIA socket that permits PCMCIA cards to be
inserted and removed during normal operation.
Features
s Bidirectional interface between 5V and 3V-to-5V buses
s Control inputs compatible with TTL level
s Outputs source/sink up to 24 mA
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
s Implements patented EMI reduction circuitry
s Flexible VCCB operating range
s Allows B Port and VCCB to float simultaneously when OE
is HIGH
s Functionally compatible with the 74 series 245
Ordering Code:
Order Number Package Number
Package Description
74LVXC4245WM
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
74LVXC4245QSC
MQA24
24-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150” Wide
74LVXC4245MTC
MTC24
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names
OE
T/R
A0–A7
B0–B7
Description
Output Enable Input
Transmit/Receive Input
Side A Inputs or 3-STATE Outputs
Side B Inputs or 3-STATE Outputs
© 1999 Fairchild Semiconductor Corporation DS012009
www.fairchildsemi.com
1 page  
AC Electrical Characteristics
CL = 50 pF
CL = 50 pF
VCCA = 4.5V to 5.5V
VCCA = 4.5V to 5.5V
Symbol
Parameter
VCCB = 4.5V to 5.5V
TA = +25°C
TA = −40°C to +85°C
VCCB = 2.7V to 3.6V
Units
TA = +25°C
TA = −40°C to +85°C
Min Typ Max Min Max Min Typ Max Min Max
(Note 6)
(Note 7)
tPHL
tPLH
tPHL
tPLH
tPZL
tPZH
Propagation
Delay A to B
Propagation
Delay B to A
Output Enable
Time OE to B
1.0 4.9 6.5
1.0 4.0 5.5
1.0 4.7 6.5
1.0 3.9 5.0
1.0 5.6 7.5
1.0 5.7 7.5
1.0
1.0
1.0
1.0
1.0
1.0
7.0 1.0 5.5 7.5 1.0
6.0 1.0 5.0 7.0 1.0
8.0
ns
7.5
7.0 1.0 5.6 7.5 1.0
5.5 1.0 4.3 6.0 1.0
8.0
ns
6.5
8.0 1.0 6.7 9.0 1.0 10.0
ns
8.0 1.0 6.9 9.5 1.0 10.0
tPZL
tPZH
Output Enable
Time OE to A
1.0 7.4 9.0
1.0
10.0
1.0
8.0 10.0 1.0
11.0
ns
1.0 6.1 7.5
1.0
8.5 1.0 6.3 8.0 1.0
8.5
tPHZ Output Disable
tPLZ Time OE to B
1.0 4.8 7.0
1.0 3.8 5.5
1.0
1.0
7.5 1.0 6.0 9.0 1.0
6.0 1.0 4.2 6.5 1.0
9.5
ns
7.0
tPHZ Output Disable
tPLZ Time OE to A
1.0 3.4 5.5
1.0 2.9 4.5
1.0
1.0
6.0 1.0 3.4 5.5 1.0
5.0 1.0 2.9 5.0 1.0
6.0
ns
5.5
tOSHL
tOSLH
Output to Output
Skew (Note 8)
Data to Output
1.0 1.5
1.5 1.0 1.5
1.5 ns
Note 6: Typical values at VCCA = 5V, VCCB = 5V @25°C.
Note 7: Typical values at VCCA = 5V, VCCB = 3.3V @25°C.
Note 8: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.
Capacitance
Symbol
Parameter
CIN Input Capacitance
CI/O Input/Output Capacitance
CPD Power Dissipation Capacitance
(Note 9)
Note 9: CPD is measured at 10 MHz.
A→B
B→A
Typ Units
Conditions
4.5 pF VCC = Open
10 pF VCCA = 5V, VCCB = 3.3V
45 pF VCCA = 5V
50 pF VCCB = 3.3V
Power Up Considerations
To insure the system does not experience unnecessary ICC
current draw, bus contention, or oscillations during power
up, the following guidelines should be adhered to (refer to
Table 1):
• Power up the control side of the device first. This is the
VCCA.
• OE should ramp with or ahead of VCCA. This will help
guard against bus contention.
• The Transmit/Receive control pin (T/R) should ramp with
VCCA, this will ensure that the A Port data pins are con-
figured as inputs. With VCCA receiving power first, the A
I/O Port should be configured as inputs to help guard
against bus contention and oscillations.
• A side data inputs should be driven to a valid logic level.
This will prevent excessive current draw.
The above steps will ensure that no bus contention or oscil-
lations, and therefore no excessive current draw occurs
during the power up cycling of these devices. These steps
will help prevent possible damage to the translator devices
and potential damage to other system components.
TABLE 1. Low Voltage Translator Power Up Sequencing Table
Device Type
VCCA
VCCB
T/R
OE
A Side I/O
B Side I/O
Floatable Pin
Allowed
74LVXC4245
5V
(power up 1st)
2.7V to 5.5V
configurable
ramp
with VCCA
ramp
with VCCA
logic
0V or VCCA
outputs
yes, VCCB and B
I/O’s w/ OE HIGH
Please reference Application Note AN-5001 for more detailed information on using Fairchild’s LVX Low Voltage Dual
Supply CMOS Translating Transceivers.
5 www.fairchildsemi.com
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