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Fairchild Semiconductor - Low Voltage Octal Transparent Latch with 3-STATE Outputs

Numéro de référence 74LVX373SJ
Description Low Voltage Octal Transparent Latch with 3-STATE Outputs
Fabricant Fairchild Semiconductor 
Logo Fairchild Semiconductor 





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74LVX373SJ fiche technique
June 1993
Revised March 1999
74LVX373
Low Voltage Octal Transparent Latch with
3-STATE Outputs
General Description
The LVX373 consists of eight latches with 3-STATE outputs
for bus organized system applications. The latches appear
transparent to the data when Latch Enable (LE) is HIGH.
When LE is LOW, the data satisfying the input timing
requirements is latched. Data appears on the bus when the
Output Enable (OE) is LOW. When OE is HIGH, the bus
output is in the high impedance state. The inputs tolerate
up to 7V allowing interface of 5V systems to 3V systems.
Features
s Input voltage translation from 5V to 3V
s Ideal for low power/low noise 3.3V applications
Ordering Code:
Order Number Package Number
Package Description
74LVX373M
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
74LVX373SJ
74LVX373MTC
M20D
MTC20
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
D0–D7
LE
OE
O0–O7
Description
Data Inputs
Latch Enable Input
Output Enable Input
3-STATE Latch Outputs
© 1999 Fairchild Semiconductor Corporation DS011613.prf
www.fairchildsemi.com

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