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PDF 74LVX161284 Data sheet ( Hoja de datos )
| Número de pieza | 74LVX161284 | |
| Descripción | Low Voltage IEEE 161284 Translating Transceiver | |
| Fabricantes | Fairchild Semiconductor | |
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January 1999
Revised July 2000
74LVX161284
Low Voltage IEEE 161284 Translating Transceiver
General Description
The LVX161284 contains eight bidirectional data buffers
and eleven control/status buffers to implement a full
IEEE 1284 compliant interface. The device supports the
IEEE 1284 standard and is intended to be used in an
Extended Capabilities Port mode (ECP). The pinout allows
for easy connection from the Peripheral (A-side) to the
Host (cable side).
Outputs on the cable side can be configured to be either
open drain or high drive (± 14 mA) and are connected to a
separate power supply pin (VCCcable) to allow these out-
puts to be driven by a higher supply voltage than the
A-side. The pull-up and pull-down series termination resis-
tance of these outputs on the cable side is optimized to
drive an external cable. In addition, all inputs (except HLH)
and outputs on the cable side contain internal pull-up resis-
tors connected to the VCCcable supply to provide proper
termination and pull-ups for open drain mode.
Outputs on the Peripheral side are standard low-drive
CMOS outputs designed to interface with 3V logic. The DIR
input controls data flow on the A1–A8/B1–B8 transceiver
pins.
Features
s Supports IEEE 1284 Level 1 and Level 2 signaling
standards for bidirectional parallel communications
between personal computers and printing peripherals
s Translation capability allows outputs on the cable side to
interface with 5V signals
s All inputs have hysteresis to provide noise margin
s B and Y output resistance optimized to drive external
cable
s B and Y outputs in high impedance mode during power
down
s Inputs and outputs on cable side have internal pull-up
resistors
s Flow-through pin configuration allows easy interface
between the “Peripheral and Host”
s Replaces the function of two (2) 74ACT1284 devices
Ordering Code
Order Number Package Number
Package Description
74LVX161284MEA
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
74LVX161284MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
Description
HD High Drive Enable Input (Active HIGH)
DIR Direction Control Input
A1–A8
B1–B8
A9–A13
Y9–Y13
A14–A17
C14–C17
PLHIN
PLH
Inputs or Outputs
Inputs or Outputs
Inputs
Outputs
Outputs
Inputs
Peripheral Logic HIGH Input
Peripheral Logic HIGH Output
HLHIN
HLH
Host Logic HIGH Input
Host Logic HIGH Output
© 2000 Fairchild Semiconductor Corporation DS500202
www.fairchildsemi.com
1 page  
AC Electrical Characteristics
TA = 0°C to +70°C
TA = −40°C to +85°C
Symbol
Parameter
VCC = 3.0V–3.6V
VCC—Cable = 3.0V–5.5V
VCC = 3.0V–3.6V
VCC—Cable = 3.0V–5.5V
Min Max Min Max
tPHL
A1–A8 to B1–B8
2.0 40.0 2.0 44.0
tPLH
A1–A8 to B1–B8
2.0 40.0 2.0 44.0
tPHL
B1–B8 to A1–A8
2.0 40.0 2.0 44.0
tPLH
B1–B8 to A1–A8
2.0 40.0 2.0 44.0
tPHL
A9–A13 to Y9–Y13
2.0 40.0 2.0 44.0
tPLH
A9–A13 to Y9–Y13
2.0 40.0 2.0 44.0
tPHL
C14–C17 to A14–A17
2.0
40.0
2.0
44.0
tPLH
C14–C17 to A14–A17
2.0
40.0
2.0
44.0
tSKEW
LH-LH or HL-HL
10.0
12.0
tPHL
PLHIN to PLH
2.0 40.0 2.0 44.0
tPLH
PLHIN to PLH
2.0 40.0 2.0 44.0
tPHL
HLHIN to HLH
2.0 40.0 2.0 44.0
tPLH
HLHIN to HLH
2.0 40.0 2.0 44.0
tPHZ Output Disable Time
2.0
15.0
2.0
18.0
tPLZ DIR to A1–A8
2.0 15.0 2.0 18.0
tPZH Output Enable Time
2.0
50.0
2.0
50.0
tPZL DIR to A1–A8
2.0 50.0 2.0 50.0
tPHZ Output Disable Time
2.0
50.0
2.0
50.0
tPLZ DIR to B1–B8
2.0 50.0 2.0 50.0
tpEN Output Enable Time
2.0
25.0
2.0
28.0
HD to B1–B8, Y9–Y13
2.0
25.0
2.0
28.0
tpDIS
Output Disable Time
2.0
25.0
2.0
28.0
HD to B1–B8, Y9–Y13
2.0
25.0
2.0
28.0
tpEN–tpDIS Output Enable-
10.0
12.0
Output Disable
tSLEW
Output Slew Rate
tPLH
B1–B8, Y9–Y13
tPHL
tr, tf tRISE and tFALL
B1–B8 (Note 8),
Y9–Y13 (Note 8)
Note 8: Open Drain
0.05 0.40 0.05 0.40
0.05 0.40 0.05 0.40
120 120
120 120
Note 9: tSKEW is measured for common edge output transitions and compares the measured propagation delay for a given path type:
(i) A1–A8 to B1–B8, A9–A13 to Y9–Y13
(ii) B1–B8 to A1–A8
(iii) C14–C17 to A14–A17
Note 10: This parameter is guaranteed but not tested, characterized only.
Units
Figure
Number
ns Figure 1
ns Figure 2
ns Figure 3
ns Figure 3
ns Figure 1
ns Figure 2
ns Figure 3
ns Figure 3
ns (Note 9)
ns Figure 1
ns Figure 2
ns Figure 3
ns Figure 3
ns Figure 7
ns Figure 8
ns Figure 9
ns Figure 2
ns Figure 2
ns
V/ns
ns
Figure 5
Figure 4
Figure 6
(Note 10)
Capacitance
Symbol
Parameter
Typ Units
Conditions
CIN Input Capacitance
3 pF VCC = 0.0V (HD, DIR, A9–A13, C14–C17, PLHIN and HLHIN)
CI/O (Note 11) I/O Pin Capacitance
5 pF VCC = 3.3V
Note 11: CI/O is measured at frequency = 1 MHz, per MIL-STD-883B, Method 3012
5 www.fairchildsemi.com
5 Page 
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
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| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet 74LVX161284.PDF ] | |
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