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PDF 74LVTH16835 Data sheet ( Hoja de datos )
| Número de pieza | 74LVTH16835 | |
| Descripción | Low Voltage 18-Bit Universal Bus Driver with 3-STATE Outputs (Preliminary) | |
| Fabricantes | Fairchild Semiconductor | |
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Preliminary
May 2000
Revised May 2000
74LVTH16835
Low Voltage 18-Bit Universal Bus Driver
with 3-STATE Outputs (Preliminary)
General Description
The LVTH16835 consists of 18-bit universal bus drivers
which combine D-type latches and D-type flip-flops to allow
data flow in transparent, latched, or clocked modes. Data
flow from A to Y is controlled by the output-enable (OE)
input. This device operates in the transparent mode when
the latch-enable (LE) input is HIGH. The A data is latched if
the clock (CLK) input is held at a HIGH or LOW logic level.
If LE is LOW, the A-bus data is stored in the latch/flip-flop
on the LOW-to-HIGH transition of the CLK. When OE is
HIGH, the outputs are in the high-impedance state.
The LVTH16835 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
The bus driver is designed for low voltage (3.3V) VCC appli-
cations, but with the capability to provide a TTL interface to
a 5V environment. The LVTH16835 is fabricated with an
advanced BiCMOS technology to achieve high speed oper-
ation similar to 5V ABT while maintaining low power dissi-
pation.
Features
s Input and output interface capability to systems at
5V VCC
s Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs
s Live insertion/extraction permitted
s Power Up/Down high impedance provides glitch-free
bus loading
s Outputs source/sink −32 mA/+64 mA
s Latch-up performance exceeds 500 mA
Ordering Code:
Order Number Package Number
Package Description
74LVTH16835MEA
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
74LVTH16835MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2000 Fairchild Semiconductor Corporation DS500102
www.fairchildsemi.com
1 page  
Preliminary
AC Electrical Characteristics
TA = −40°C to +85°C, CL = 50 pF, RL = 500 Ω
Symbol
Parameter
VCC = 3.3 ± 0.3V
VCC = 2.7V
Units
Min Max Min Max
fMAX
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tS
Propagation Delay
A to Y
Propagation Delay
LE to Y
Propagation Delay
CLK to Y
Output Enable Time
Output Disable Time
Setup Time
150 150 MHz
1.3 3.7 1.3 4.0
ns
1.3 3.7 1.3 4.0
1.5 5.1 1.5 5.7
ns
1.5 5.1 1.5 5.7
1.5 5.1 1.5 5.7
ns
1.5 5.1 1.5 5.7
1.3 4.6 1.3 5.5
ns
1.3 4.6 1.3 5.5
1.7 5.8 1.7 6.3
ns
1.7 5.8 1.7 6.3
A before CLK 2.1
2.4
A before LE, CLK HIGH 2.3
1.5
ns
A before LE, CLK LOW 1.5
0.5
tH Hold Time
A after CLK
A after LE
1.0
0.8
0.0
0.8
ns
tW Pulse Duration
LE HIGH
CLK HIGH or LOW
3.3
3.3
3.3
3.3
ns
tOSLH
tOSHL
Output to Output Skew
(Note 10)
1.0 1.0
ns
1.0 1.0
Note 10: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Capacitance (Note 11)
Symbol
Parameter
Conditions
CIN Input Capacitance
VCC = 0V, VI = 0V or VCC
COUT
Output Capacitance
VCC = 3.0V, VO = 0V or VCC
Note 11: Capacitance is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012.
Typical
4
8
Units
pF
pF
5 www.fairchildsemi.com
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet 74LVTH16835.PDF ] | |
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| 74LVTH16835 | Low Voltage 18-Bit Universal Bus Driver with 3-STATE Outputs (Preliminary) | Fairchild Semiconductor |
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