74LVTH16500MTD Datasheet PDF - Fairchild Semiconductor
| Part Number | 74LVTH16500MTD | |
| Description | Low Voltage 18-Bit Universal Bus Transceivers with 3-STATE Outputs Preliminary | |
| Manufacturers | Fairchild Semiconductor | |
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Preliminary
May 2000
Revised May 2000
74LVTH16500
Low Voltage 18-Bit Universal Bus Transceivers
with 3-STATE Outputs (Preliminary)
General Description
The LVTH16500 is an 18-bit universal bus transceiver
combining D-type latches and D-type flip-flops to allow
data flow in transparent, latched, and clocked modes.
Data flow in each direction is controlled by output-enable
(OEAB and OEBA), latch-enable (LEAB and LEBA), and
clock (CLKAB and CLKBA) inputs.
The LVTH16500 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
The transceiver is designed for low voltage (3.3V) VCC
applications, but with the capability to provide a TTL inter-
face to a 5V environment. The LVTH16500 is fabricated
with an advanced BiCMOS technology to achieve high
speed operation similar to 5V ABT while maintaining low
power dissipation.
Features
s Input and output interface capability to systems at
5V VCC
s Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs
s Live insertion/extraction permitted
s Power Up/Down high impedance provides glitch-free
bus loading
s Outputs source/sink −32 mA/+64 mA
s Functionally compatible with the 74 series 16500
s Latch-up performance exceeds 500 mA
Ordering Code:
Order Number Package Number
Package Description
74LVTH16500MEA
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
74LVTH16500MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix “X” to the ordering code.
© 2000 Fairchild Semiconductor Corporation DS012447
www.fairchildsemi.com
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Preliminary
AC Electrical Characteristics
Symbol
fMAX
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tSU
Propagation Delay
Data to Outputs
Propagation Delay
LEBA or LEAB to B or A
Propagation Delay
CLKBA or CLKAB to B or A
Output Enable Time
Output Disable Time
Setup Time
Parameter
TA = −40°C to +85°C, CL = 50 pF, RL = 500 Ω
VCC = 3.3 ± 0.3V
VCC = 2.7V
Min Max Min Max
150 150
1.3 3.7 1.3 4.0
1.3 3.7 1.3 4.0
1.5 5.1 1.5 5.7
1.5 5.1 1.5 5.7
1.3 5.0 1.3 5.9
1.3 5.0 1.3 5.9
1.3 4.8 1.3 5.5
1.3 4.8 1.3 5.5
1.7 5.8 1.7 6.3
1.7 5.8 1.7 6.3
A before CLKAB 2.9
2.9
B before CLKBA 2.9
2.9
A or B before LE, CLK HIGH 1.4
0.5
Units
MHz
ns
ns
ns
ns
ns
ns
A or B before LE, CLK LOW 2.9
2.3
tH Hold Time
A or B after CLK
A or B after LE
0.4
1.6
0.4
1.6
ns
tW Pulse Duration
LE HIGH
CLK HIGH or LOW
3.3
3.3
3.3
3.3
ns
tOSLH
tOSHL
Output to Output Skew (Note 11)
1.0 1.0
ns
1.0 1.0
Note 11: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Capacitance (Note 12)
Symbol
Parameter
Conditions
CIN Input Capacitance
VCC = 0V, VI = 0V or VCC
CI/O Input/Output Capacitance
VCC = 3.0V, VO = 0V or VCC
Note 12: Capacitance is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012.
Typical
4
8
Units
pF
pF
5 www.fairchildsemi.com
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