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PDF 74LVQ573T Data sheet ( Hoja de datos )
| Número de pieza | 74LVQ573T | |
| Descripción | OCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS NON INVERTING | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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® 74LVQ573
OCTAL D-TYPE LATCH
WITH 3 STATE OUTPUTS NON INVERTING
s HIGH SPEED: tPD = 5 ns (TYP.) at VCC = 3.3V
s COMPATIBLE WITH TTL OUTPUTS
s LOW POWER DISSIPATION:
ICC = 4 µA (MAX.) at TA = 25 oC
s LOW NOISE:
VOLP = 0.5 V (TYP.) at VCC = 3.3V
s 75Ω TRANSMISSION LINE DRIVING
CAPABILITY
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24 mA (MIN)
s PCI BUS LEVELS GUARANTEED AT 24mA
s BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
s OPERATING VOLTAGE RANGE:
VCC (OPR) = 2V to 3.6V (1.2V Data Retention)
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 573
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The LVQ573 is a low voltage CMOS OCTAL
D-TYPE LATCH with 3 STATE OUTPUT NON
INVERTING fabricated with sub-micron silicon
gate and double-layer metal wiring C2MOS
technology. It is ideal for low power and low
noise 3.3V applications.
These 8 bit D-Type flip-flops are controlled by a
latch enable input (LE) and an output enable
PIN CONNECTION AND IEC LOGIC SYMBOLS
M
(Micro Package)
T
(TSSOP Package)
ORDER CODES :
74LVQ573M
74LVQ573T
input (OE).
While the LE input is held at a high level, the Q
outputs will follow the data input precisely.
When the LE is taken low, the Q outputs will be
latched precisely at the logic level of D input data.
While the (OE) input is low, the 8 outputs will be
in a normal logic state (high or low logic level)
and while high level the outputs will be in a high
impedance state.
It has better speed performance at 3.3V than 5V
LSTTL family combined with the true CMOS low
power consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
February 1999
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1 page  
74LVQ573
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = tf =3 ns)
Symb ol
Parameter
T est Con ditio n
VCC
(V)
Valu e
TA = 25 oC
-40 to 85 oC
Min. T yp. Max. Min. Max.
Unit
tPLH Propagation Delay Time
tPHL LE to Q
2.7
3.3(*)
8.0 17.0
6.5 11.0
18.0
12.0
ns
tPLH Propagation Delay Time
tPHL D to Q
2.7
3.3(*)
7.5 15.0
6.0 10.0
16.0
11.0
ns
tPLZ Output Disable Time
tPHZ
2.7
3.3(*)
8.5 20.0
7.0 14.0
21.0
15.0
ns
tPZL Output Enable Time
tPZH
2.7
3.3(*)
9.0 18.0
7.0 12.0
19.0
13.0
ns
tw LE pulse Width, HIGH
2.7
3.3(*)
2.0 5.0
1.5 4.0
6.0 ns
4.0
tsL Setup Time D to LE
tsH HIGH or LOW
2.7
3.3(*)
0.0 2.5
0.0 2.0
3.0 ns
2.5
thL Hold Time D to LE,
thH HIGH or LOW
2.7
3.3(*)
0.0 2.5
0.0 2.0
3.0 ns
2.5
tOSLZ Output to Output Skew
tOSHL Time (note 1, 2)
2.7
3.3(*)
0.5 1.0
0.5 1.0
1.5 ns
1.5
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any twooutputs of the same device switching in the
same direction, either HIGH or LOW (tOSLH = |tPLHm - tPLHn|, tOSHL = |tPHLm - tpHLn|)
2) Parameter guaranteed by design
(*) Voltage range is 3.3V ± 0.3V
CAPACITIVE CHARACTERISTICS
Symb ol
Parameter
Test Conditions
VCC
(V)
Valu e
TA = 25 oC
-40 to 85 oC
Min. T yp. Max. Min. Max.
Unit
CIN Input Capacitance
3.3
4 pF
COUT Output Capacitance
3.3
10 pF
CPD Power Dissipation
3.3 fIN = 10 MHz
Capacitance (note 1)
10
pF
1) CPD isdefined as the value of the IC’sinternal equivalent capacitance which is calculated fromthe operating current consumption without load. (Referto
Test Circuit).Average operting current can be obtained by the following equation. ICC(opr) = CPD • VCC •fIN + ICC/* (per Latch)
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| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet 74LVQ573T.PDF ] | |
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