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PDF 74LVQ32M Data sheet ( Hoja de datos )

Número de pieza 74LVQ32M
Descripción QUAD 2-INPUT OR GATE
Fabricantes STMicroelectronics　
Logotipo STMicroelectronics Logotipo



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No Preview Available ! 74LVQ32M Hoja de datos, Descripción, Manual

74LVQ32
QUAD 2-INPUT OR GATE
s HIGH SPEED: tPD = 5 ns (TYP.) at VCC = 3.3V
s COMPATIBLEWITH TTL OUTPUTS
s LOW POWER DISSIPATION:
ICC = 2 µA (MAX.) at TA = 25 oC
s LOW NOISE:
VOLP = 0.3 V (TYP.) at VCC = 3.3V
s 75Ω TRANSMISSION LINE DRIVING
CAPABILITY
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 12 mA (MIN)
s PCI BUS LEVELS GUARANTEED AT 24mA
s BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
s OPERATING VOLTAGE RANGE:
VCC (OPR) = 2V to 3.6V (1.2V Data Retention)
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 32
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The LVQ32 is a low voltage CMOS QUAD
2-INPUT OR GATE fabricated with sub-micron
silicon gate and double-layer metal wiring C2MOS
M
(Micro Package)
T
(TSSOP Package)
ORDER CODES :
74LVQ32M
74LVQ32T
technology. It is ideal for low power and low noise
3.3V applications.
The internal circuit is composed of 2 stages
including buffer output, which enables high noise
immunity and stable output.
It has better speed performance at 3.3V than 5V
LS-TTL family combined with the true CMOS low
power consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
February 1999
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74LVQ32M pdf
TEST CIRCUIT
74LVQ32
CL = 50 pF or equivalent (includes jigand probe capacitance)
RL = R1 = 500Ω orequivalent
RT = ZOUT of pulse generator (typically 50Ω)
WAVEFORM: PROPAGATION DELAYS (f=1MHz; 50% duty clycle)
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