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PDF 74LVQ138 Data sheet ( Hoja de datos )
| Número de pieza | 74LVQ138 | |
| Descripción | 3 TO 8 LINE DECODER INVERTING | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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® 74LVQ138
3 TO 8 LINE DECODER (INVERTING)
s HIGH SPEED: tPD = 5.5 ns (TYP.) at VCC = 3.3V
s COMPATIBLE WITH TTL OUTPUT
s LOW POWER DISSIPATION:
ICC = 4 µA (MAX.) at TA = 25 oC
s LOW NOISE:
VOLP = 0.2 V (TYP.) at VCC = 3.3V
s 75Ω TRANSMISSION LINE DRIVING
CAPABILITY
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 12 mA (MIN)
s PCI BUS LEVELS GUARANTEED AT 24mA
s BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
s OPERATING VOLTAGE RANGE:
VCC (OPR) = 2V to 3.6V (1.2V Data Retention)
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 138
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The LVQ138 is a low voltage CMOS 3 TO 8 LINE
DECODER (INVERTING) fabricated with
sub-micron silicon gate and double-layer metal
wiring C2MOS technology.
It is ideal for low power and low noise 3.3V
applications.
M1
(Micro Package)
T
(TSSOP Package)
ORDER CODES :
74LVQ138M
74LVQ138T
If the device is enabled, 3 binary select inputs (A,
B and C) determine which one of the outputs will
go low. If enable input G1 is held low or either
G2A or G2B is held high, the decoding function is
inhibited and all the 8 outputs go high.
Three enable inputs are provided to ease
cascade connection and application of address
decoders for memory systems.
It has better speed performance at 3.3V than 5V
LSTTL family combinad with the true CMOS low
power consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
February 1999
1/9
1 page  
74LVQ138
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = tf =3 ns)
Symb ol
Parameter
T est Con ditio n
VCC
(V)
Valu e
TA = 25 oC
-40 to 85 oC
Min. T yp. Max. Min. Max.
Unit
tPLH Propagation Delay Time
tPHL A, B, C to Y
2.7
3.3(*)
7.0 17.0
5.5 12.0
20.0
14.0
ns
tPLH Propagation Delay Time
tPHL G1 to Y
2.7
3.3(*)
7.0 17.0
5.5 12.0
20.0
14.0
ns
tPLH Propagation Delay Time
tPHL G2A or G2B to Y
2.7
3.3(*)
7.0 17.0
5.5 12.0
20.0
14.0
ns
tOSLH Output to Output Skew
tOSHL Time (note 1, 2)
2.7
3.3(*)
0.5 1.5
0.5 1.5
1.5 ns
1.5
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any twooutputs of the same device switching in the
same direction, either HIGH or LOW (tOSLH = |tPLHm - tPLHn|, tOSHL = |tPHLm - tpHLn|)
2) Parameter guaranteed by design
(*) Voltage range is 3.3V ± 0.3V
CAPACITIVE CHARACTERISTICS
Symb ol
Parameter
Test Conditions
VCC
(V)
Valu e
TA = 25 oC
-40 to 85 oC
Min. T yp. Max. Min. Max.
Unit
CIN Input Capacitance
3.3
5 pF
CPD Power Dissipation
3.3 fIN = 10 MHz
Capacitance (note 1)
50
pF
1) CPD isdefined as the value of the IC’sinternal equivalent capacitance which is calculated fromthe operating current consumption without load. (Referto
Test Circuit).Average operting current can be obtained by the following equation. ICC(opr) = CPD • VCC • fIN + ICC
TEST CIRCUIT
CL = 50 pF or equivalent (includes jigand probe capacitance)
RL = R1 = 500Ω orequivalent
RT = ZOUT of pulse generator (typically 50Ω)
5/9
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet 74LVQ138.PDF ] | |
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