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PDF 74LVQ125 Data sheet ( Hoja de datos )
| Número de pieza | 74LVQ125 | |
| Descripción | QUAD BUS BUFFERS 3-STATE | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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® 74LVQ125
QUAD BUS BUFFERS (3-STATE)
s HIGH SPEED: tPD = 5 ns (TYP.) at VCC = 3.3V
s COMPATIBLE WITH TTL OUTPUTS
s LOW POWER DISSIPATION:
ICC = 4 µA (MAX.) at TA = 25 oC
s LOW NOISE:
VOLP = 0.3 V (TYP.) at VCC = 3.3V
s 75Ω TRANSMISSION LINE DRIVING
CAPABILITY
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 12 mA (MIN)
s PCI BUS LEVELS GUARANTEED AT 24mA
s BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
s OPERATING VOLTAGE RANGE:
VCC (OPR) = 2V to 3.6V (1.2V Data Retention)
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 125
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The LVQ125 is a low voltage CMOS QUAD BUS
BUFFERS fabricated with sub-micron silicon gate
and double-layer metal wiring C2MOS
M
(Micro Package)
T
(TSSOP Package)
ORDER CODES :
74LVQ125M
74LVQ125T
technology. It is ideal for low power and low noise
3.3V applications.
The device requires the same 3-STATE control
input G to be set high to place the output in to the
high impedance state.
It has better speed performance at 3.3V than 5V
LS-TTL family combined with the true CMOS low
power consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
February 1999
1/8
1 page  
WAVEFORM 1: PROPAGATION DELAYS (f=1MHz; 50% duty cycle)
74LVQ125
WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle)
5/8
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet 74LVQ125.PDF ] | |
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