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PDF 74LVC74APWDH Data sheet ( Hoja de datos )
| Número de pieza | 74LVC74APWDH | |
| Descripción | Dual D-type flip-flop with set and reset; positive-edge trigger | |
| Fabricantes | NXP Semiconductors | |
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INTEGRATED CIRCUITS
74LVC74A
Dual D-type flip-flop with set and reset;
positive-edge trigger
Product specification
IC24 Data Handbook
1998 Jun 17
Philips
Semiconductors
1 page  
Philips Semiconductors
Dual D-type flip-flop with set and reset;
positive-edge trigger
Product Specification
74LVC74A
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions voltages are referenced to GND (ground = 0V)
SYMBOL
PARAMETER
TEST CONDITIONS
VIH HIGH level Input voltage
VCC = 1.2V
VCC = 2.7 to 3.6V
VIL LOW level Input voltage
VCC = 1.2V
VCC = 2.7 to 3.6V
VCC = 2.7V; VI = VIH or VIL; IO = –12mA
VOH HIGH level output voltage
VCC = 3.0V; VI = VIH or VIL; IO = –100µA
VCC = 3.0V; VI = VIH or VIL; IO = –18mA
VCC = 3.0V; VI = VIH or VIL; IO = –24mA
VCC = 2.7V; VI = VIH or VIL; IO = 12mA
VOL LOW level output voltage
VCC = 3.0V; VI = VIH or VIL; IO = 100µA
VCC = 3.0V; VI = VIH or VIL; IO = 24mA
II Input leakage current
VCC = 3.6V; VI = 5.5V or GND
ICC Quiescent supply current
VCC = 3.6V; VI = VCC or GND; IO = 0
∆ICC
Additional quiescent supply current per
input pin
VCC = 2.7V to 3.6V; VI = VCC –0.6V; IO = 0
NOTES:
1. All typical values are at VCC = 3.3V and Tamb = 25°C.
LIMITS
Temp = -40°C to +85°C
MIN TYP1 MAX
VCC
2.0
GND
0.8
VCC*0.5
VCC*0.2
VCC*0.6
VCC*1.0
VCC
0.40
GND 0.20
0.55
"0.1 "5
0.1 10
UNIT
V
V
V
V
µA
µA
5 500 µA
AC CHARACTERISTICS
GND = 0 V; tr = tf v 2.5 ns; CL = 50 pF; RL = 500W; Tamb = –40_C to +85_C
SYMBOL
PARAMETER
WAVEFORM
Propagation delay
nCP to nQ, nQ
tPHL/
tPLH
tW
Propagation delay
nSD to nQ, nQ
Propagation delay
nRD to nQ, nQ
Clock pulse width HIGH or LOW
Set or reset pulse width LOW
trem Removal time set or reset
tsu Set-up time nD to nCP
th Hold time nD to nCP
fmax Maximum clock pulse frequency
NOTE:
1. These typical values are at VCC = 3.3V and Tamb = 25°C.
Figures 1, 3
Figures 2, 3
Figures 2, 3
Figure 1
Figure 2
Figure 2
Figure 1
Figure 1
Figure 1
LIMITS
VCC = 3.3V ±0.3V
MIN TYP1 MAX
1.5 3.6 5.2
1.5 3.5 5.4
1.5 3.5 5.4
3.3 1.3
3.3 1.7
1 –3
2.0 0.8
1 –0.7
150 250
–
–
–
–
–
–
VCC = 2.7V
MIN MAX
– 6.0
– 6.4
– 6.4
––
––
––
––
––
––
UNIT
ns
ns
ns
ns
ns
ns
ns
MHz
1998 Jun 17
5
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet 74LVC74APWDH.PDF ] | |
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