|
|
PDF 74LVC374A Data sheet ( Hoja de datos )
| Número de pieza | 74LVC374A | |
| Descripción | Octal D-type flip-flop | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de 74LVC374A (archivo pdf) en la parte inferior de esta página. Total 19 Páginas | ||
|
No Preview Available !
74LVC374A
Octal D-type flip-flop; 5 V tolerant inputs/outputs;
positive-edge trigger; 3-state
Rev. 3 — 6 December 2012
Product data sheet
1. General description
The 74LVC374A is an octal D-type flip-flop featuring separate D-type inputs for each
flip-flop and 3-state outputs for bus-oriented applications. A clock input (CP) and an
outputs enable input (OE) are common to all flip-flops.
The eight flip-flops will store the state of their individual D-inputs that meet the set-up and
hold times requirements on the LOW-to-HIGH CP transition.
When pin OE is LOW, the contents of the eight flip-flops is available at the outputs. When
pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE
input does not affect the state of the flip-flops.
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be
applied to the outputs. These features allow the use of these devices as translators in
mixed 3.3 V and 5 V applications.
The 74LVC374A is functionally identical to the 74LVC574A, but has a different pin
arrangement.
2. Features and benefits
5 V tolerant inputs/outputs; for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
High-impedance when VCC = 0 V
8-bit positive edge-triggered register
Independent register and 3-state buffer operation
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from 40 C to +85 C and 40 C to +125 C
1 page  
NXP Semiconductors
74LVC374A
Octal D-type flip-flop; 5 V tolerant inputs/outputs; positive-edge trigger; 3-state
6. Functional description
Table 3. Function table[1]
Operating mode
Input
OE
Load and read register
L
L
Load register and disable
outputs
H
H
CP
Dn
l
h
l
h
[1] H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition
Z = high-impedance OFF-state
= LOW-to-HIGH clock transition
7. Limiting values
Internal flip-flop Output
Qn
LL
HH
LZ
HZ
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min Max
Unit
VCC supply voltage
0.5 +6.5
V
IIK
input clamping current
VI < 0 V
50 -
mA
VI input voltage
[1] 0.5
+6.5
V
IOK
output clamping current
VO > VCC or VO < 0 V
- 50
mA
VO output voltage
output HIGH or LOW state
[2] 0.5
VCC + 0.5 V
output 3-state
[2] 0.5
+6.5
V
IO
ICC
IGND
Tstg
Ptot
output current
supply current
ground current
storage temperature
total power dissipation
VO = 0 V to VCC
Tamb = 40 C to +125 C
-
-
100
65
[3] -
50
100
-
+150
500
mA
mA
mA
C
mW
[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.
[2] The output voltage ratings may be exceeded if the output current ratings are observed.
[3] For SO20 packages: above 70 C the value of Ptot derates linearly with 8 mW/K.
For SSOP20 and TSSOP20 packages: above 60 C the value of Ptot derates linearly with 5.5 mW/K.
For DHVQFN20 packages: above 60 C the value of Ptot derates linearly with 4.5 mW/K.
74LVC374A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 6 December 2012
© NXP B.V. 2012. All rights reserved.
5 of 19
5 Page 
NXP Semiconductors
74LVC374A
Octal D-type flip-flop; 5 V tolerant inputs/outputs; positive-edge trigger; 3-state
VI
negative
pulse
0V
VI
positive
pulse
0V
90 %
10 %
VM
10 %
tf
tr
90 %
VM
tW
tW
VM
tr
tf
VM
VI
G
VCC
DUT
VO
VEXT
RL
RT CL RL
001aae331
Test data is given in Table 9.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 10. Load circuitry for switching times
Table 9. Test data
Supply voltage
VCC
1.2 V
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
3.0 V to 3.6 V
Input
VI
VCC
VCC
VCC
2.7 V
2.7 V
tr, tf
2 ns
2 ns
2 ns
2.5 ns
2.5 ns
Load
CL
30 pF
30 pF
30 pF
50 pF
50 pF
RL
1 k
1 k
500
500
500
VEXT
tPLH, tPHL
open
open
open
open
open
tPLZ, tPZL
2 VCC
2 VCC
2 VCC
2 VCC
2 VCC
tPHZ, tPZH
GND
GND
GND
GND
GND
74LVC374A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 6 December 2012
© NXP B.V. 2012. All rights reserved.
11 of 19
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet 74LVC374A.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| 74LVC374A | Octal D-type flip-flop | NXP Semiconductors |
| 74LVC374A | Octal D-type flip-flop |  Philips |
| 74LVC374A | OCTAL D-TYPE FLIP-FLOP |  STMicroelectronics |
| 74LVC374A | OCTAL D-TYPE FLIP-FLOP |  Diodes |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |