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PDF 74LVC2G32 Data sheet ( Hoja de datos )
| Número de pieza | 74LVC2G32 | |
| Descripción | Dual 2-input OR gate | |
| Fabricantes | NXP Semiconductors | |
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74LVC2G32
Dual 2-input OR gate
Rev. 11 — 8 April 2013
Product data sheet
1. General description
The 74LVC2G32 provides a 2-input OR gate function.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these
devices as translators in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing a damaging backflow current through the device
when it is powered down.
2. Features and benefits
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant outputs in the Power-down mode
High noise immunity
24 mA output drive (VCC = 3.0 V)
CMOS low power consumption
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8-B/JESD36 (2.7 V to 3.6 V)
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C
1 page  
NXP Semiconductors
74LVC2G32
Dual 2-input OR gate
8. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min Max
Unit
VCC supply voltage
VI input voltage
VO output voltage
Active mode
Power-down mode
0.5
[1] 0.5
[1] 0.5
[2] 0.5
+6.5
+6.5
VCC + 0.5
+6.5
V
V
V
V
IIK
IOK
IO
ICC
IGND
Tstg
Ptot
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
VI < 0 V
VO < 0 V or VO > VCC
VO = 0 V to VCC
Tamb = 40 C to +125 C
50
-
-
-
100
65
[3] -
-
50
50
100
-
+150
300
mA
mA
mA
mA
mA
C
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal condition.
[3] For TSSOP8 package: above 55 C the value of Ptot derates linearly with 2.5 mW/K.
For VSSOP8 package: above 110 C the value of Ptot derates linearly with 8 mW/K.
For XSON8 and XQFN8 packages: above 118 C the value of Ptot derates linearly with 7.8 mW/K.
9. Recommended operating conditions
Table 6.
Symbol
VCC
VI
VO
Operating conditions
Parameter
supply voltage
input voltage
output voltage
Tamb
t/V
ambient temperature
input transition rise and fall rate
Conditions
Active mode
Power-down mode
VCC = 1.65 V to 2.7 V
VCC = 2.7 V to 5.5 V
Min Max Unit
1.65 5.5
V
0 5.5 V
0
VCC
V
0 5.5 V
40
+125
C
- 20 ns/V
- 10 ns/V
74LVC2G32
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 11 — 8 April 2013
© NXP B.V. 2013. All rights reserved.
5 of 21
5 Page 
NXP Semiconductors
74LVC2G32
Dual 2-input OR gate
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm
SOT765-1
D
y
Z
8
5
pin 1 index
E
c
HE
A A2
A1
1
e
4
bp w M
detail X
A
X
vM A
Q
(A3)
θ
Lp
L
0 2.5 5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c D(1) E(2) e
mm
1
0.15
0.00
0.85
0.60
0.12
0.27
0.17
0.23
0.08
2.1
1.9
2.4
2.2
0.5
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
HE
3.2
3.0
OUTLINE
VERSION
SOT765-1
IEC
REFERENCES
JEDEC
JEITA
MO-187
L Lp Q v w y Z(1) θ
0.4
0.40 0.21
0.15 0.19
0.2
0.13
0.1
0.4
0.1
8°
0°
EUROPEAN
PROJECTION
ISSUE DATE
02-06-07
Fig 11. Package outline SOT765-1 (VSSOP8)
74LVC2G32
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 11 — 8 April 2013
© NXP B.V. 2013. All rights reserved.
11 of 21
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet 74LVC2G32.PDF ] | |
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