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PDF M48T58 Data sheet ( Hoja de datos )
| Número de pieza | M48T58 | |
| Descripción | 64 Kbit (8 Kb x 8) TIMEKEEPER SRAM | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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M48T58
M48T58Y
5.0 V, 64 Kbit (8 Kb x 8) TIMEKEEPER® SRAM
Features
■ Integrated, ultra low power SRAM, real-time
clock, power-fail control circuit and battery
■ BYTEWIDE™ RAM-like clock access
■ BCD coded year, month, day, date, hours,
minutes, and seconds
■ Frequency test output for real-time clock
■ Automatic power-fail chip deselect and WRITE
protection
■ WRITE protect voltages
(VPFD = power-fail deselect voltage):
– M48T58: VCC = 4.75 to 5.5 V;
4.5 V ≤ VPFD ≤ 4.75 V
– M48T58Y: VCC = 4.5 to 5.5 V;
4.2 V ≤ VPFD ≤ 4.5 V
■ Self-contained battery and crystal in the
CAPHAT™ DIP package
■ Packaging includes a 28-lead SOIC and
SNAPHAT® top (to be ordered separately)
■ SOIC package provides direct connection for a
snaphat housing containing the battery and
crystal
■ Pin and function compatible with JEDEC
standard 8 Kb x 8 SRAMs
■ RoHS compliant
– Lead-free second level interconnect
28
1
PCDIP28
Battery/crystal
CAPHAT™
SNAPHAT®
Battery/crystal
28
1
SOH28
June 2011
Doc ID 2412 Rev 8
1/33
www.st.com
1
1 page  
M48T58, M48T58Y
1 Description
Description
The M48T58/Y TIMEKEEPER® RAM is a 8 Kb x 8 non-volatile static RAM and real-time
clock. The monolithic chip is available in two special packages to provide a highly integrated
battery-backed memory and real-time clock solution.
The M48T58/Y is a non-volatile pin and function equivalent to any JEDEC standard
8b Kb x 8 SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets,
providing the non-volatility of PROMs without any requirement for special WRITE timing or
limitations on the number of WRITEs that can be performed.
The 28-pin, 600 mil DIP CAPHAT™ houses the M48T58/Y silicon with a quartz crystal and a
long life lithium button cell in a single package.
The 28-pin, 330 mil SOIC provides sockets with gold plated contacts at both ends for direct
connection to a separate SNAPHAT® housing containing the battery and crystal. The
unique design allows the SNAPHAT battery package to be mounted on top of the SOIC
package after the completion of the surface mount process. Insertion of the SNAPHAT
housing after reflow prevents potential battery and crystal damage due to the high
temperatures required for device surface-mounting. The SNAPHAT housing is keyed to
prevent reverse insertion. The SOIC and battery/crystal packages are shipped separately in
plastic anti-static tubes or in tape & reel form.
For the 28-lead SOIC, the battery/crystal package (e.g., SNAPHAT) part number is “M4T28-
BR12SH”.
Figure 1. Logic diagram
VCC
13
A0-A12
8
DQ0-DQ7
W
M48T58
E1 M48T58Y FT
E2
G
VSS
AI01374B
Doc ID 2412 Rev 8
5/33
5 Page 
M48T58, M48T58Y
4 WRITE mode
WRITE mode
The M48T58/Y is in the WRITE mode whenever W and E1 are low and E2 is high. The start
of a WRITE is referenced from the latter occurring falling edge of W or E1, or the rising edge
of E2. A WRITE is terminated by the earlier rising edge of W or E1, or the falling edge of E2.
The addresses must be held valid throughout the cycle. E1 or W must return high or E2 low
for a minimum of tE1HAX or tE2LAX from chip enable or tWHAX from WRITE enable prior to the
initiation of another READ or WRITE cycle. Data-in must be valid tDVWH prior to the end of
WRITE and remain valid for tWHDX afterward. G should be kept high during WRITE cycles to
avoid bus contention; although, if the output bus has been activated by a low on E1 and G
and a high on E2, a low on W will disable the outputs tWLQZ after W falls.
Figure 6. WRITE enable controlled, WRITE AC waveform
A0-A12
E1
E2
W
DQ0-DQ7
tAVE1L
tAVAV
VALID
tAVWH
tWHAX
tAVE2H
tAVWL
tWLWH
tWLQZ
tWHDX
DATA INPUT
tDVWH
tWHQX
AI00963
Doc ID 2412 Rev 8
11/33
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet M48T58.PDF ] | |
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