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PDF M48T512V Data sheet ( Hoja de datos )
| Número de pieza | M48T512V | |
| Descripción | 4 Mbit (512 Kbit x 8) TIMEKEEPER SRAM | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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M48T512Y
M48T512V
5.0 or 3.3 V, 4 Mbit (512 Kbit x 8) TIMEKEEPER® SRAM
Not recommended for new design
Features
■ Integrated ultra low power SRAM, real-time
clock, power-fail control circuit, battery, and
crystal
)■ BCD coded year, month, day, date, hours,
t(sminutes, and seconds
c■ Automatic power-fail chip deselect and WRITE
uprotection
rod■ WRITE protect voltages:
(VPFD = power-fail deselect voltage)
P– M48T512Y: VCC = 4.5 to 5.5 V;
te4.2 V ≤ VPFD ≤ 4.5 V
le– M48T512V: VCC = 3.0 to 3.6 V;
so2.7 V ≤ VPFD ≤ 3.0 V
b■ Conventional SRAM operation; unlimited
OWRITE cycles
-■ Software controlled clock calibration for high
t(s)accuracy applications
■ 10 years of data retention and clock operation
ucin the absence of power
d■ Pin and function compatible with industry
rostandard 512 K x 8 SRAMS
P■ Self-contained battery and crystal in DIP
tepackage
le■ RoHS compliant
Obso– Lead-free second level interconnect
32
1
PMDIP32 module
June 2011
Doc ID 5747 Rev 7
This is information on a product still in production but not recommended for new designs.
1/23
www.st.com
1
1 page  
M48T512Y, M48T512V
1 Description
Description
The M48T512Y/V TIMEKEEPER® RAM is a 512 Kb x 8 non-volatile static RAM and real-
time clock organized as 524,288 words by 8 bits. The special DIP package provides a fully
integrated battery-backed memory and real-time clock solution.
The M48T512Y/V directly replaces industry standard 512 Kb x 8 SRAMs. It also provides
the non-volatility of Flash without any requirement for special WRITE timing or limitations on
the number of WRITEs that can be performed.
Figure 1. Logic diagram
VCC
ct(s)19
uA0-A18
rodW
te PE
leG
M48T512Y
M48T512V
8
DQ0-DQ7
ct(s) - ObsoTable 1. Signal names
duA0-A18
roDQ0-DQ7
PE
teG
oleW
Obs VCC
VSS
Address inputs
Data inputs / outputs
Chip enable input
Output enable input
WRITE enable input
Supply voltage
AI02262
VSS Ground
Doc ID 5747 Rev 7
5/23
5 Page 
M48T512Y, M48T512V
3 Clock operations
Clock operations
3.1 Reading the clock
Updates to the TIMEKEEPER® registers should be halted before clock data is read to
prevent reading data in transition (see Table 5 on page 12). The BiPORT™ TIMEKEEPER
cells in the RAM array are only data registers and not the actual clock counters, so updating
the registers can be halted without disturbing the clock itself.
Updating is halted when a '1' is written to the READ bit, D6 in the control register (7FFF8h).
As long as a '1' remains in that position, updating is halted. After a halt is issued, the
roduct(s)3.2
Obsolete PNote:
t(s) -3.3
Obsolete ProducNote:
registers reflect the count; that is, the day, date, and time that were current at the moment
the halt command was issued. All of the TIMEKEEPER registers are updated
simultaneously. A halt will not interrupt an update in progress. The next update occurs 1
second after the READ bit is reset to a '0.'
Setting the clock
Bit D7 of the control register (7FFF8h) is the WRITE bit. Setting the WRITE bit to a '1,' like
the READ bit, halts updates to the TIMEKEEPER registers. The user can then load them
with the correct day, date, and time data in 24 hour BCD format (see Table 5 on page 12).
Resetting the WRITE bit to a '0' then transfers the values of all time registers 7FFFFh-
7FFF9h to the actual TIMEKEEPER counters and allows normal operation to resume. After
the WRITE bit is reset, the next clock update will occur approximately one second later.
Upon power-up, both the WRITE bit and the READ bit will be reset to '0.'
Stopping and starting the oscillator.
The oscillator may be stopped at any time. If the device is going to spend a significant
amount of time on the shelf, the oscillator can be turned off to minimize current drain on the
battery. The STOP bit is located at bit D7 within 7FFF9h. Setting it to a '1' stops the
oscillator. The M48T512Y/V is shipped from STMicroelectronics with the STOP bit set to a
'1.' When reset to a '0,' the M48T512Y/V oscillator starts after approximately one second.
It is not necessary to set the WRITE bit when setting or resetting the FREQUENCY TEST
bit (FT) or the STOP bit (ST).
Doc ID 5747 Rev 7
11/23
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet M48T512V.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| M48T512V | 4 Mbit (512 Kbit x 8) TIMEKEEPER SRAM | ST Microelectronics |
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