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PDF M48T212Y Data sheet ( Hoja de datos )
| Número de pieza | M48T212Y | |
| Descripción | 5V/3.3V TIMEKEEPER[ CONTROLLER | |
| Fabricantes | ST Microelectronics | |
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M48T212Y
M48T212V
5V/3.3V TIMEKEEPER® CONTROLLER
s CONVERTS LOW POWER SRAM into
NVRAMs
s YEAR 2000 COMPLIANT (4-Digit Year)
s BATTERY LOW FLAG
s INTEGRATED REAL TIME CLOCK,
POWER-FAIL CONTROL CIRCUIT, BATTERY
and CRYSTAL
s AUTOMATIC POWER-FAIL CHIP DESELECT
and WRITE PROTECTION
s WATCHDOG TIMER
s CHOICE of WRITE PROTECT VOLTAGES
(VPFD = Power-fail Deselect Voltage):
– M48T212Y: 4.2V ≤ VPFD ≤ 4.5V
– M48T212V: 2.7V ≤ VPFD ≤ 3.0V
s MICROPROCESSOR POWER-ON RESET
s PROGRAMMABLE ALARM OUTPUT ACTIVE
in the BATTERY BACKED-UP MODE
s PACKAGING INCLUDES a 44-LEAD SOIC and
SNAPHAT® TOP (to be Ordered Separately)
DESCRIPTION
The M48T212Y/V are self-contained devices that
include a real time clock (RTC), programmable
alarms, a watchdog timer, and two external chip
enable outputs which provide control of up to four
(two in parallel) external low-power static RAMs.
Access to all TIMEKEEPER® functions and the
external RAM is the same as conventional byte-
wide SRAM. The 16 TIMEKEEPER Registers offer
Century, Year, Month, Date, Day, Hour, Minute,
Second, Calibration, Alarm, Watchdog, and Flags.
Externally attached static RAMs are controlled by
the M48T212Y/V via the E1CON and E2CON sig-
nals (see Table 4).
The 44 pin 330mil SOIC provides sockets with
gold plated contacts at both ends for direct con-
nection to a separate SNAPHAT housing contain-
ing the battery and crystal. The unique design
allows the SNAPHAT battery package to be
mounted on top of the SOIC package after the
completion of the surface mount process.
SNAPHAT (SH)
Battery
44
1
SOH44 (MH)
Figure 1. Logic Diagram
VCC VCCSW
4
A0-A3
A
E
EX
W
G
WDI
RSTIN1
RSTIN2
M48T212Y
M48T212V
8
DQ0-DQ7
IRQ/FT
RST
E1CON
E2CON
VOUT
VSS
AI03019
April 2000
1/23
1 page  
M48T212Y, M48T212V
Table 6. Capacitance (1)
(TA = 25 °C, f = 1 MHz)
Symbol
Parameter
CIN Input Capacitance
COUT (2) Input/Output Capacitance
Note: 1. Sampled only, not 100% tested.
2. Outputs deselected.
Test Condit ion
VIN = 0V
VOUT = 0V
Min Max Unit
10 pF
10 pF
Table 7A. DC Characteristics for M48T212V
(TA = 0 to 70°C; VCC = 3V to 3.6V)
Symbol
Parameter
Test Condition
Min
Typ
Max Unit
ILI (1,2) Input Leakage Current
0V ≤ VIN ≤ VCC
±1 µA
ILO (1) Output Leakage Current
0V ≤ VOUT ≤ VCC
±1 µA
ICC Supply Current
Outputs open
4 10 mA
ICC1 Supply Current (Standby) TTL
E = VIH
3 mA
ICC2 Supply Current (Standby) CMOS
E = VCC –0.2
2 mA
Battery Current OSC ON
IBAT
Battery Current OSC OFF
575 800 nA
100 nA
VIL Input Low Voltage
–0.3 0.8 V
VIH Input High Voltage
2.0 VCC + 0.3 V
Output Low Voltage
VOL
Output Low Voltage (open drain) (3)
IOL = 2.1mA
IOL = 10mA
0.4 V
0.4 V
VOH Output High Voltage
IOH = –1.0mA
2.4
V
VOHB (4) VOH Battery Back-up
IOUT2 = –1.0µA
2.0
3.6 V
IOUT1 (5) VOUT Current (Active)
VOUT1 > VCC –0.3
70 mA
IOUT2 VOUT Current (Battery Back-up)
VOUT2 > VBAT –0.3
100 µA
VPFD Power-fail Deselect Voltage
2.7 2.9
3.0 V
VSO Battery Back-up Switchover Voltage
VPFD –100mV
V
VBAT Battery Voltage
3.0 V
Note: 1. Outputs deselected.
2. RSTIN1 and RSTIN2 internally pulled-up to VCC through 100KΩ resistor. WDI internally pulled-down to VSS through 100KΩ resistor.
3. For IRQ/FT & RST pins (Open Drain).
4. Conditioned outputs (E1CON - E2CON) can only sustain CMOS leakage currents in the battery back-up mode. Higher leakage cur-
rents will reduce battery life.
5. External SRAM must match TIMEKEE PER Controller chip VCC specification.
5/23
5 Page 
M48T212Y, M48T212V
Table 11. Write Mode AC Characteristics
(TA = 0 to 70°C)
M48T212Y
M48T212V
Symbol
Parameter
-70 -85
Min Max Min Max
tAVAV Write Cycle Time
70 85
tAVWL Address Valid to Write Enable Low
0
0
tAVEL Address Valid to Chip Enable Low
0
0
tWLWH Write Enable Pulse Width
45 55
tELEH Chip Enable Low to Chip Enable High
50
60
tWHAX Write Enable High to Address Transition
0
0
tEHAX Chip Enable High to Address Transition
0
0
tDVWH Input Valid to Write Enable High
25
30
tDVEH Input Valid to Chip Enable High 25 30
tWHDX Write Enable High to Input Transition
0
0
tEHDX Chip Enable High to Input Transition
0
0
tWLQZ (1,2) Write Enable Low to Output High-Z
20 25
tAVWH Address Valid to Write Enable High
55
65
tAVEH Address Valid to Chip Enable High
55
65
tWHQX (1,2) Write Enable High to Output Transition
5
5
Note: 1. CL = 5pF.
2. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DATA RETENTION MODE
With valid VCC applied, the M48T212Y/V can be
accessed as described above with read or write
cycles. Should the supply voltage decay, the
M48T212Y/V will automatically deselect, write
protecting itself (and any external SRAM) when
VCC falls between VPFD (max) and VPFD (min).
This is accomplished by internally inhibiting ac-
cess to the clock registers via the E signal. At this
time, the Reset pin (RST) is driven active and will
remain active until VCC returns to nominal levels.
External RAM access is inhibited in a similar man-
ner by forcing E1CON and E2CON to a high level.
This level is within 0.2 volts of the VBAT. E1CON
and E2CON will remain at this level as long as VCC
remains at an out-of tolerance condition.
When VCC falls below the level of the battery
(VBAT), power input is switched from the VCC pin
to the SNAPHAT battery and the clock registers
and external SRAM are maintained from the at-
tached battery supply. All outputs become high im-
pedance. The VOUT pin is capable of supplying
100µA of current to the attached memory with less
than 0.3V drop under this condition. On power up,
when VCC returns to a nominal value, write protec-
tion continues for 200ms (max) by inhibiting
E1CON or E2CON.
The RST signal also remains active during this
time (see Figure 5).
Note: Most low power SRAMs on the market to-
day can be used with the M48T212Y/V TIME-
KEEPER Controller. There are, however some
criteria which should be used in making the final
choice of an SRAM to use. The SRAM must be de-
signed in a way where the chip enable input dis-
ables all other inputs to the SRAM. This allows
inputs to the M48T212Y/V and SRAMs to be Don’t
Care once VCC falls below VPFD(min). The SRAM
should also guarantee data retention down to
VCC = 2.0V. The chip enable access time must be
sufficient to meet the system needs with the chip
enable output propagation delays included.
11/23
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet M48T212Y.PDF ] | |
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