PDF M41T256YMT7 Data sheet ( Hoja de datos )

Número de pieza	M41T256YMT7
Descripción	256 Kbit 32K x8 SERIAL RTC
Fabricantes	ST Microelectronics
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No Preview Available ! www.DataSheet4U.com M41T256Y 256 Kbit (32K x8) Serial RTC FEATURES SUMMARY ■ 5V OPERATING VOLTAGE ■ SERIAL INTERFACE SUPPORTS EXTENDED I2C BUS ADDRESSING (400kHz) ■ AUTOMATIC SWITCH-OVER AND DESELECT CIRCUITRY ■ POWER-FAIL DESELECT VOLTAGES: – M41T256Y: VCC = 4.5 to 5.5V; VPFD = 4.2 < VPFD < 4.5V ■ COUNTERS FOR TENTHS/HUNDREDTHS OF SECONDS, SECONDS, MINUTES, HOURS, DAY, DATE, MONTH, and YEAR ■ PROGRAMMABLE SOFTWARE CLOCK CALIBRATION ■ 32,752 BYTES OF GENERAL PURPOSE RAM ■ MICROPROCESSOR POWER-ON RESET ■ HOLDS MICROPROCESSOR IN RESET UNTIL SUPPLY VOLTAGE REACHES STABLE OPERATING LEVEL ■ AUTOMATIC ADDRESS-INCREMENTING ■ TAMPER INDICATION CIRCUIT WITH TIME- STAMP ■ SLEEP MODE FUNCTION ■ PACKAGING INCLUDES A 44-LEAD SOIC AND SNAPHAT® TOP (to be ordered separately) ■ SOIC PACKAGE PROVIDES DIRECT CONNECTION FOR A SNAPHAT® TOP WHICH CONTAINS THE BATTERY AND CRYSTAL Figure 1. 44-pin, Hatless SOIC Package 44 1 SO44 (MT) Figure 2. 44-pin SOIC Package SNAPHAT (SH) Crystal/Battery 44 1 SOH44 (MH) June 2004 1/27 1 page Figure 4. 44-pin SOIC Connections (MT) XO XI NF RST NF NF NF NF NF NF NF TP NC NF NF NF NF SDA VSS VSS NC VSS 1 44 2 43 3 42 4 41 5 40 6 39 7 38 8 37 9 36 10 35 11 M41T256Y 34 12 33 13 32 14 31 15 30 16 29 17 28 18 27 19 26 20 25 21 24 22 23 VCC NC NC NC FT NF NF NF NF NF NF NC NC NF SCL NC NF NF NF NF NF BAT+ AI04755b Note: No Function (NF) must be tied to VSS. Figure 6. Block Diagram SDA SCL PULL-UP TO CHIP VCC I2C INTERFACE Crystal TP 32KHz OSCILLATOR VCC M41T256Y Figure 5. 44-pin SOIC (MH - SNAPHAT) NC NC NF RST NF NF NF NF NF NF NF TP NC NF NF NF NF SDA VSS VSS NC VSS 1 44 2 43 3 42 4 41 5 40 6 39 7 38 8 37 9 36 10 35 11 M41T256Y 34 12 33 13 32 14 31 15 30 16 29 17 28 18 27 19 26 20 25 21 24 22 23 VCC NC NC NC FT NF NF NF NF NF NF NC NC NF SCL NC NF NF NF NF NF NC AI07022 REAL TIME CLOCK CALENDAR 32,752 BYTES USER RAM RTC & CALIBRATION TAMPER BIT FT(1) POWER VBAT Note: 1. Open drain output VBL= 2.5V COMPARE VSO = VBAT COMPARE VPFD = 4.38V COMPARE BL POR RST(1) AI04759 5/27 5 Page M41T256Y WRITE Mode In this mode the master transmitter transmits to the M41T256Y slave receiver. Bus protocol is shown in Figure 13., page 11. Following the START condition and slave address, a logic '0' (R/ W=0) is placed on the bus and indicates to the ad- dressed device that byte addresses A(0) and A(1) will follow and is to be written to the on-chip ad- dress pointer (MSB of address byte A(0) is a “Don’t care”). The data byte to be written to the memory is strobed in next and the internal address pointer is incremented to the next memory location within the RAM on the reception of an acknowledge bit. The M41T256Y slave receiver will send an ac- knowledge bit to the master transmitter after it has received the slave address (see Figure 10., page 9) and again after it has received each address byte. Figure 13. WRITE Mode Sequence BUS ACTIVITY: MASTER SDA LINE S BYTE BYTE ADDRESS (0) ADDRESS (1) DATA n BUS ACTIVITY: SLAVE ADDRESS DATA n+X P AI04761 11/27 11 Page

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