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PDF M39208 Data sheet ( Hoja de datos )
| Número de pieza | M39208 | |
| Descripción | Single Chip 2 Mbit Flash and 64 Kbit Parallel EEPROM Memory | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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M39208
Single Chip 2 Mbit Flash and 64 Kbit Parallel EEPROM Memory
2.7V to 3.6V SUPPLY VOLTAGE for
PROGRAM, ERASE and READ OPARATIONS
100ns ACCESS TIME
(Flash and EEPROM blocks)
WRITE, PROGRAM and ERASE STATUS BITS
CONCURRENT MODE (Read Flash while
writing to EEPROM)
100,000 ERASE/WRITE CYCLES
10 YEARS DATA RETENTION
LOW POWER CONSUMPTION
– Stand-by mode: 60µA
– Automatic Stand-by mode
– Deep Power Down mode
64 bytes ONE TIME PROGRAMMABLE
MEMORY
STANDARD EPROM/OTP MEMORY
PACKAGE
EXTENDED TEMPERATURE RANGES
PRELIMINARY DATA
TSOP32 (NA)
8 x 20 mm
TSOP32 (NB)
8 x 14 mm
Figure 1. Logic Diagram
DESCRIPTION
The M39208 is a memory device combining Flash
and EEPROM into a single chip and using single
supply voltage. The memory is mapped in two
blocks: 2 Mbit of Flash memory and 64 Kbit of
EEPROM memory. Each space is independant for
writing, in concurrent mode the Flash Memory can
be read while the EEPROM is being written.
Table 1. Signal Names
A0-A17
Address Inputs
DQ0-DQ7 Data Input / Outputs
EE EEPROM Block Enable
EF Flash Block Enable
G Output Enable
W Write Enable
VCC Supply Voltage
VSS Ground
VCC
18
A0-A17
W
EE
EF
G
M39208
8
DQ0-DQ7
VSS
AI02589
February 1999
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1/30
1 page  
M39208
Table 4. Instructions (1)
Instruction
EE EF Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7
Read Manufacturer
Identifier (2)
Read
1
0
AAh
@5555h
55h
@2AAAh
90h
@5555h
Identifier
with
(A0,A1,A6)
at (0,0,0)
Read Flash
Identifier (2)
Read
1
0
AAh
@5555h
55h
@2AAAh
90h
@5555h
identifier
with
(A0,A1,A6)
at (1,0,0)
Read OTP Row
0
1
AAh 55h 90h
@5555h @2AAAh @5555h
Read
byte 1
Read
byte 2
Read
byte N
Read Block
Protection Status (2)
Read
1
0
AAh
@5555h
55h
@2AAAh
90h
@5555h
Identifier
with
(A0,A1,A6)
at (0,1,0)
Program a Flash Byte 1
0
AAh 55h A0h Data
@5555h @2AAAh @5555h @address
Erase one Flash
Block
1
0
AAh
@5555h
55h
@2AAAh
80h
@5555h
AAh
@5555h
55h
@2AAAh
30h
@Sector
address
30h
@Sector
address(3)
Erase the Whole Flash 1
0
AAh 55h 80h AAh 55h 10h
@5555h @2AAAh @5555h @5555h @2AAAh @5555h
Suspend Block Erase 1
B0h
0 @any
address
30h
Resume Block Erase 1 0 @any
address
EEPROM Power
Down
0
1
AAh 55h 30h
@5555h @2AAAh @5555h
Deep Power Down
1
0
20h
@5555h
SDP Enable
(EEPROM)
0
1
AAh 55h A0h
@5555h @2AAAh @5555h
Write
byte 1
Write
byte 2
Write
byte N
SDP Disable
(EEPROM)
0
1
AAh 55h 80h AAh 55h 20h
@5555h @2AAAh @5555h @5555h @2AAAh @5555h
Write in OTP Row
0
1
AAh 55h B0h
@5555h @2AAAh @5555h
Write
byte 1
Write
byte 2
Write
byte N
Return (from OTP
Read or EEPROM
Power Down)
F0h @
01
any
address
Reset
1
0
AAh
@5555h
55h
@2AAAh
F0h
@any
Address
Reset (short
instruction)
F0h
1 0 @any
address
Notes: 1. AAh @5555h means Write byte AAh at address 5555h.
2. This instruction can also be performed as a simple Read operation with A9=VID (refer to READ chapter).
3. Additional blocks to be erased must be entered within 80µs.
5/30
5 Page 
M39208
Data Polling. Polling on DQ7 is a method of check-
ing whether a Program or an Erase instruction is in
progress or completed (see Figure 6). When a
Program instruction is in progress, data bit DQ7 is
the complement of the original data bit 7; when
DQ7 is identical to the old data and the Error bit
DQ5 is still ’0’, the instruction is complete. To de-
termine if DQ7 is valid, each poll must store the
original data for comparison, and if they are the
same, it can be considered that the operation was
successful. The Error bit DQ5 is checked to ensure
timing limits have not exceeded.
When an Erase operation is in progress, DQ7 is
always ’0’, and will be ’1’ when finished, so long as
DQ5= ’0’.
In all cases, when DQ5 is ’1’, DQ7 should be
checked again, in case DQ7 changed simultane-
ously with DQ5. If DQ7 = true data (Program) or
DQ7 = ’1’ (Erase), the operation is successful and
execution should return to the caller. A suggested
second read will provide all true data (Program) or
all FFh (Erase). Otherwise, this should be flagged
as an error, and the device should be Reset.
Data Toggle. Checking the Toggle bit DQ6 is an
alternative method of checking if Program or Erase
operations are in progress or completed (see Fig-
ure 7). When an operation is in progress, data bit
DQ6 constantly toggles for successive read opera-
tions. When DQ6 no longer toggles and the Error
bit DQ5 is ’0’, the operation is completed. To deter-
mine if DQ6 has toggled, each polling action re-
quires 2 consecutive read operations of the data,
and if the data read is the same, it can be consid-
ered that the operation was successful. The Error
bit DQ5 is checked to ensure timing limits have not
been exceeded. In all cases, when DQ5 is ’1’, DQ6
should be checked again, in case DQ6 has
changed simultaneously with DQ5. If DQ6 has
stopped toggling, the operation is successful and
execution should return to the caller. A suggested
second read will provide all true data (Program) or
all FFh (Erase). Otherwise, this event should be
flagged as an error, and the device should be
Reset.
ERASE in the Flash BLOCK
It should be noted that:
a. Programming any byte of one Flash sector (or
bulk) requires that the Flash sector (or bulk) has
been previously erased (once for all bytes within
the sector or bulk) with the correct instruction (see
Instructions chapter).
b. Writing in the EEPROM memory is an operation
triggering an automatic sequencing of byte erase
followed by a byte write. Writing in EEPROM does
not require a specific erase operation before writ-
ing.
Bulk Erase Instruction. The Bulk Erase instruc-
tion uses six write operations followed by Read
operations of the status register bits, as described
in Table 4. If any byte of the Bulk Erase instruction
is wrong, the Bulk Erase instruction aborts and the
device is reset to the Read Flash memory status.
During a Bulk Erase, the memory status may
checked by reading the status bits DQ5, DQ6 and
DQ7, as detailed in the "PROGRAM in the Flash
BLOCK" chapter. The Error bit (DQ5) returns a ’1’
if there has been an Erase Failure (maximum num-
ber of erase cycles have been executed).
It is not necessary to program the array with 00h,
the M39208 will automatically do this before eras-
ing to FFh.
During the execution of the Bulk Erase instruction,
the Flash block logic does not accept any instruc-
tion.
Sector Erase in Flash Block. The Sector Erase
instruction uses six write operations, as described
in Table 4. Additional Flash Sector Erase confirm
commands and Flash sector addresses can written
subsequently to erase other Flash sectors in par-
allel, without further coded cycles, if the additional
instruction is transmited in a shorter time than the
timeout period to end of period. The input of a new
Sector Erase instruction will restart the time-out
period.
The status of the internal timer can be monitored
through the level of DQ3 (Erase time-out bit), if DQ3
is ’0’ the Sector Erase instruction has been re-
ceived and the timeout is counting; if DQ3 is ’1’, the
timeout has expired and the M39208 is erasing the
Flash sector(s). Before and during Erase timeout,
any instruction different than Erase suspend and
Erase Resume will abort the instruction and reset
the device to read array mode.
It is not necessary to program the Flash sector with
00h as the M39208 will do this automatically before
erasing (byte = FFh).
During a Sector Erase, the memory status may be
checked by reading the status bits DQ5, DQ6 and
DQ7, as detailed in the "Program instruction" chap-
ter. During the execution of the erase instruction,
the Flash block logic accepts only the Reset and
Erase Suspend instructions (erasure of one Flash
sector may be suspended, in order to read data
from another Flash sector, and then resumed).
11/30
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet M39208.PDF ] | |
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