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PDF MAX1101 Data sheet ( Hoja de datos )
| Número de pieza | MAX1101 | |
| Descripción | Single-Chip / 8-Bit CCD Digitizer with Clamp and 6-Bit PGA | |
| Fabricantes | Maxim Integrated | |
| Logotipo |  |
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19-1166; Rev 0; 12/96
Single-Chip, 8-Bit CCD Digitizer
with Clamp and 6-Bit PGA
_______________General Description
The MAX1101 is a highly integrated IC designed pri-
marily for digitizing the output of a linear CCD array. It
provides the components required for all necessary
analog functions, including clamp circuitry for black-
level correction or correlated double sampling (CDS), a
three-input multiplexer (mux), and an 8-bit analog-to-
digital converter (ADC).
The MAX1101 operates with a sample rate up to 1MHz
and with a wide range of linear CCDs. The logic inter-
face is serial, and a single input sets the bidirectional
data line as either data in or data out, thus minimizing
the I/O pins required for communication.
Packaged in a 24-pin SO, the MAX1101 is available in
the commercial (0°C to +70°C) temperature range.
____________________________Features
o 1.0 Million Pixels/sec Conversion Rate
o Built-In Clamp Circuitry for Black-Level
Correction or Correlated Double Sampling
o 64-Step PGA, Programmable from Gain = -2 to -10
o Auxiliary Mux Inputs for Added Versatility
o Compatible with a Large Range of CCDs
o 8-Bit ADC Included
o Space-Saving, 24-Pin SO Package
________________________Applications
Scanners
Fax Machines
Digital Copiers
CCD Imaging
______________Ordering Information
PART
MAX1101CWG
TEMP. RANGE
0°C to +70°C
PIN-PACKAGE
24 Wide SO
Pin Configuration appears on last page.
___________________________________________________Typical Operating Circuit
CCD
ARRAY
CEXT
0.047µF
0.1µF
12
AUXILIARY
ANALOG INPUTS
1 GND
GND 24
2 CCDIN
3
GND
4 AIN1
5 GND
MAX1101 VDD 23
22
CLAMP
VIDSAMP 21
20
LOAD
6 AIN2
7 GND
11 REFGND
DATA
SCLK
MODE
GND
VDD
REFBIAS
19
18
17
16
15
14
12
REF-
13
REF+
0.1µF
+5V DC (SUPPLY)
µP/µC/
STATE LOGIC
+5V DC (REFERENCE)
0.1µF
________________________________________________________________ Maxim Integrated Products 1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
1 page  
Single-Chip, 8-Bit CCD Digitizer
with Clamp and 6-Bit PGA
REF+
CLAMP
FROM
CCD
CEXT
0.047µF
S2
REF+
S1
CI
REF-
S1
CF
S2
S1P
TO
ADC
REF-
VIDSAMP
S1*
S2*
S1P*
ON OFF
OFF ON
OFF ON
* INTERNALLY GENERATED SIGNALS
Figure 2. PGA Functional Diagram
Programmable-Gain Amplifier
The PGA amplifies the differential video signal from the
CCD (at CCDIN). Gain is settable with the 6-bit con-
trol word from -2 to -10 in 64 steps, in increments of
-0.125. The PGA also provides for periodic DC restora-
tion of the capacitively coupled input.
As shown in Figure 2, the switched-capacitor amplifier’s
gain is set by the ratio CI/CF. The input is sampled on
the CI capacitors, which is a set of equal capacitors.
The 6-bit gain control word determines the number
of capacitors used. Thus the PGA gain is set from
-2 to -10.
A voltage equal to VREF- is applied to the PGA’s nonin-
verting input. This offsets the PGA output to be within
the range of the ADC (VREF- to VREF+).
Clamp Circuit
As shown in Figure 2, the CCD output is connected to
the MAX1101 input (CCDIN) through an external
capacitor, which removes the potentially large DC
common-mode voltages from the input signal.
Whenever CLAMP is high, the CLAMP switch is closed
and CEXT is charged to VREF+. It can be actuated
either once per pixel (sampling reset level) or less fre-
quently (such as for restoring optical black level once
per line), as required by the application.
REF+ REF-
CF
CI
VOUT = VREF- ±V0S
REF-
Figure 3a. PGA Connection with VIDSAMP = Low
VREF+
- VVIDEO
(FROM DC
RESTORE)
CI
CF
REF-
Figure 3b. PGA Connection with VIDSAMP = High
VIDSAMP controls the sampling of the video signal
and offset nulling of the PGA. To null out the offset,
VIDSAMP causes switches S1 and S1P to close, plac-
ing the amplifier in a unity-gain configuration, as shown
in Figure 3a. This configuration causes the amplifier’s
offset voltage to be stored on CF. In the next portion of
the cycle, when VIDSAMP returns low, the S1 switches
are opened and S2 is closed (Figure 3b). This is the
standard inverting op-amp configuration. The only dif-
ference is that capacitors are used to set the gain, and
the amplifier’s offset voltage has been stored on these
capacitors and is thus canceled. The amplifier’s output
is [CF/CI] x VVIDEO + VREF-. The CDS function is shown
in Figure 4.
ADC
The ADC uses a recycling half-flash conversion tech-
nique in which a 4-bit flash ADC section achieves an
8-bit result in two steps (Figure 5). Using 15 compara-
tors, the flash ADC compares the unknown input
voltage to the reference ladder (using REF+ and REF-)
and provides the upper four data bits.
An internal digital-to-analog converter (DAC) uses the
four most significant bits (MSBs) to generate the analog
result from the first flash conversion and a residue volt-
age that is the difference between the unknown voltage
_______________________________________________________________________________________ 5
5 Page 
Single-Chip, 8-Bit CCD Digitizer
with Clamp and 6-Bit PGA
__________________Pin Configuration
100.00
TOP VIEW
10.00
1.00
0.10
0.01
3
45 67 89
NUMBER OF TIME CONSTANTS
10
Figure 13. Black Level Error vs. CEXT Time Constant at
Maximum PGA Gain (1mV/bit)
Bypassing and Layout Considerations
Solder the MAX1101 to a multilayer board (two or more
layers) where the layer immediately beneath the device
is a ground plane.
Connect the VDD pins together at the MAX1101. Connect
all ground pins together at the device.
Bypass VDD to ground with at least a 0.1µF ceramic
capacitor. If larger capacitors are used, tantalum is
satisfactory.
GND 1
CCDIN 2
GND 3
AIN1 4
GND 5
AIN2 6
GND 7
I.C. 8
I.C. 9
I.C. 10
REFGND 11
REF- 12
MAX1101
SO
24 GND
23 VDD
22 BLKSAMP
21 VIDSAMP
20 LOAD
19 DATA
18 SCLK
17 MODE
16 GND
15 VDD
14 REFBIAS
13 REF+
___________________Chip Information
TRANSISTOR COUNT: 3430
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet MAX1101.PDF ] | |
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