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PDF MAX1090 Data sheet ( Hoja de datos )
| Número de pieza | MAX1090 | |
| Descripción | 10-Bit ADCs | |
| Fabricantes | Maxim Integrated | |
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19-1640; Rev 2; 12/02
EVAALVUAAILTAIOBNLEKIT
400ksps, +5V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
General Description
The MAX1090/MAX1092 low-power, 10-bit analog-to-
digital converters (ADCs) feature a successive-approxi-
mation ADC, automatic power-down, fast wake-up
(2µs), an on-chip clock, +2.5V internal reference, and a
high-speed, byte-wide parallel interface. The devices
operate with a single +5V analog supply and feature a
VLOGIC pin that allows them to interface directly with a
+2.7V to +5.5V digital supply.
Power consumption is only 10mW (VDD = VLOGIC) at a
400ksps max sampling rate. Two software-selectable
power-down modes enable the MAX1090/MAX1092 to
be shut down between conversions; accessing the par-
allel interface returns them to normal operation.
Powering down between conversions can cut supply
current to under 10µA at reduced sampling rates.
Both devices offer software-configurable analog inputs
for unipolar/bipolar and single-ended/pseudo-differen-
tial operation. In single-ended mode, the MAX1090 has
eight input channels and the MAX1092 has four input
channels (four and two input channels, respectively,
when in pseudo-differential mode).
Excellent dynamic performance and low power, com-
bined with ease of use and small package size, make
these converters ideal for battery-powered and data-
acquisition applications or for other circuits with demand-
ing power consumption and space requirements.
The MAX1090/MAX1092 tri-states INT when CS goes
high. Refer to the MAX1060/MAX1064 if tri-stating INT is
not desired.
The MAX1090 is available in a 28-pin QSOP package,
while the MAX1092 comes in a 24-pin QSOP. For pin-
compatible +3V, 10-bit versions, refer to the MAX1091/
MAX1093 data sheet.
Applications
Industrial Control Systems
Data Logging
Energy Management
Data-Acquisition Systems
Patient Monitoring
Touchscreens
Ordering Information
PART
TEMP RANGE PIN-PACKAGE
INL
(LSB)
MAX1090ACEI 0°C to +70°C
MAX1090BCEI 0°C to +70°C
MAX1090AEEI -40°C to +85°C
MAX1090BEEI -40°C to +85°C
28 QSOP
28 QSOP
28 QSOP
28 QSOP
±0.5
±1
±0.5
±1
Ordering Information continued at end of data sheet.
Features
o 10-Bit Resolution, ±0.5 LSB Linearity
o +5V Single-Supply Operation
o User-Adjustable Logic Level (+2.7V to +5.5V)
o Internal +2.5V Reference
o Software-Configurable Analog Input Multiplexer
8-Channel Single-Ended/
4-Channel Pseudo-Differential (MAX1090)
4-Channel Single-Ended/
2-Channel Pseudo-Differential (MAX1092)
o Software-Configurable Unipolar/Bipolar Analog
Inputs
o Low Current: 2.5mA (400ksps)
1.0mA (100ksps)
400µA (10ksps)
2µA (Shutdown)
o Internal 6MHz Full-Power Bandwidth Track/Hold
o Byte-Wide Parallel (8 + 2) Interface
o Small Footprint: 28-Pin QSOP (MAX1090)
24-Pin QSOP (MAX1092)
Pin Configurations
TOP VIEW
HBEN 1
D7 2
D6 3
D5 4
D4 5
D3 6
D2 7
D1/D9 8
D0/D8 9
INT 10
RD 11
WR 12
MAX1092
QSOP
24 VLOGIC
23 VDD
22 REF
21 REFADJ
20 GND
19 COM
18 CH0
17 CH1
16 CH2
15 CH3
14 CS
13 CLK
Pin Configurations continued at end of data sheet.
Typical Operating Circuits appear at end of data sheet.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
400ksps, +5V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
TIMING CHARACTERISTICS (continued)
(VDD = VLOGIC = +5V ±10%, COM = GND, REFADJ = VDD, VREF = +2.5V, 4.7µF capacitor at REF pin, fCLK = 7.6MHz (50% duty
cycle), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
CS Rise to Output Disable
RD Rise to Output Disable
RD Fall to Output Data Valid
HBEN Rise to Output Data Valid
HBEN Fall to Output Data Valid
RD Fall to INT High Delay
CS Fall to Output Data Valid
SYMBOL
tTC
tTR
tDO
tDO1
tDO1
tINT1
tDO2
CONDITIONS
CLOAD = 20pF, Figure 1
CLOAD = 20pF, Figure 1
CLOAD = 20pF, Figure 1
CLOAD = 20pF, Figure 1
CLOAD = 20pF, Figure 1
CLOAD = 20pF, Figure 1
CLOAD = 20pF, Figure 1
MIN TYP MAX UNITS
10 60 ns
10 40 ns
10 50 ns
10 50 ns
10 80 ns
50 ns
100 ns
Note 1: Tested at VDD = +5V, COM = GND, unipolar single-ended input mode.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after offset and gain errors have
been removed.
Note 3: Offset nulled.
Note 4: On channel is grounded; sine wave applied to off channels.
Note 5: Conversion time is defined as the number of clock cycles times the clock period; clock has 50% duty cycle.
Note 6: Input voltage range referenced to negative input. The absolute range for the analog inputs is from GND to VDD.
Note 7: External load should not change during conversion for specified accuracy.
Note 8: When bit 5 is set low for internal acquisition, WR must not return low until after the first falling clock edge of the conversion.
DOUT
3kΩ
CLOAD
20pF
VLOGIC
3kΩ
DOUT
CLOAD
20pF
a) HIGH-Z TO VOH AND VOL TO VOH
b) HIGH-Z TO VOL AND VOH TO VOL
Figure 1. Load Circuits for Enable/Disable Times
_______________________________________________________________________________________ 5
5 Page 
400ksps, +5V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
initiate a combined acquisition plus conversion. The sam-
pling interval occurs at the end of the acquisition interval.
The ACQMOD (acquisition mode) bit in the input control
byte (Table 1) offers two options for acquiring the signal:
an internal and an external acquisition. The conversion
period lasts for 13 clock cycles in either the internal or
external clock or acquisition mode. Writing a new control
byte during a conversion cycle aborts the conversion and
starts a new acquisition interval.
Internal Acquisition
Select internal acquisition by writing the control byte
with the ACQMOD bit cleared (ACQMOD = 0). This
causes the write pulse to initiate an acquisition interval
whose duration is internally timed. Conversion starts
when this acquisition interval (three external clock
cycles or approximately 1µs in internal clock mode)
ends (Figure 4). When the internal acquisition is com-
bined with the internal clock, the aperture jitter can be
as high as 200ps. Internal clock users wishing to
achieve the 50ps jitter specification should always use
external acquisition mode.
External Acquisition
Use external acquisition mode for precise control of the
sampling aperture and/or dependent control of acquisi-
tion and conversion times. The user controls acquisition
and start-of-conversion with two separate write pulses.
The first pulse, written with ACQMOD = 1, starts an
acquisition interval of indeterminate length. The second
write pulse, written with ACQMOD = 0 (all other bits in
the control byte are unchanged), terminates acquisition
and starts conversion on WR rising edge (Figure 5).
The address bits for the input multiplexer must have the
same values on the first and second write pulses.
Power-down mode bits (PD0, PD1) can assume new
values on the second write pulse (see the Power-Down
Modes section). Changing other bits in the control byte
corrupts the conversion.
Reading a Conversion
A standard interrupt signal, INT, is provided to allow the
MAX1090/MAX1092 to flag the µP when the conversion
has ended and a valid result is available. INT goes low
when the conversion is complete and the output data is
ready (Figures 4 and 5). INT returns high on the first
read cycle or if a new control byte is written.
Selecting Clock Mode
The MAX1090/MAX1092 operate with an internal or
external clock. Control bits D6 and D7 select either
internal or external clock mode. The part retains the
last-requested clock mode if a power-down mode is
selected in the current input word. For both internal and
external clock modes, internal or external acquisition
can be used. At power-up, the MAX1090/MAX1092
enter the default external clock mode.
Table 1. Control Byte Functional Description
BIT
D7, D6
D5
D4
D3
D2, D1, D0
NAME
FUNCTION
PD1 and PD0 select the various clock and power-down modes.
0 0 Full Power-Down Mode. Clock mode is unaffected.
PD1, PD0
0
1 Standby Power-Down Mode. Clock mode is unaffected.
1 0 Normal Operation Mode. Internal clock mode is selected.
1 1 Normal Operation Mode. External clock mode is selected.
ACQMOD
SGL/DIF
UNI/BIP
A2, A1, A0
ACQMOD = 0: Internal Acquisition Mode
ACQMOD = 1: External Acquisition Mode
SGL/DIF = 0: Pseudo-Differential Analog Input Mode
SGL/DIF = 1: Single-Ended Analog Input Mode
In single-ended mode, input signals are referred to COM. In pseudo-differential mode, the voltage
difference between two channels is measured (Tables 2 and 3).
UNI/BIP = 0: Bipolar Mode
UNI/BIP = 1: Unipolar Mode
In unipolar mode, an analog input signal from 0 to VREF can be converted; in bipolar mode, the
signal can range from -VREF/2 to +VREF/2.
Address bits A2, A1, A0 select which of the 8/4 (MAX1090/MAX1092) channels is to be converted
(Tables 3 and 4).
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet MAX1090.PDF ] | |
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