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PDF MAX106 Data sheet ( Hoja de datos )
| Número de pieza | MAX106 | |
| Descripción | 8-Bit ADC | |
| Fabricantes | Maxim Integrated | |
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19-1486; Rev 1; 11/01
±5V, 600Msps, 8-Bit ADC with On-Chip
2.2GHz Bandwidth Track/Hold Amplifier
General Description
The MAX106 PECL-compatible, 600Msps, 8-bit analog-to-
digital converter (ADC) allows accurate digitizing of ana-
log signals with bandwidths to 2.2GHz. Fabricated on
Maxim’s proprietary advanced GST-2 bipolar process, the
MAX106 integrates a high-performance track/hold (T/H)
amplifier and a quantizer on a single monolithic die.
The innovative design of the internal T/H, which has an
exceptionally wide 2.2GHz full-power input bandwidth,
results in high, 7.6 effective bits performance at the
Nyquist frequency. A fully differential comparator design
and decoding circuitry combine to reduce out-of-
sequence code errors (thermometer bubbles or sparkle
codes) and provide excellent metastable performance of
one error per 1027 clock cycles. Unlike other ADCs, which
can have errors that result in false full- or zero-scale out-
puts, the MAX106 limits the error magnitude to 1LSB.
The analog input is designed for either differential or sin-
gle-ended use with a ±250mV input voltage range. Dual,
differential, PECL-compatible output data paths ensure
easy interfacing and include an 8:16 demultiplexer feature
that reduces output data rates to one-half the sampling
clock rate. The PECL outputs can be operated from any
supply between +3V to +5V for compatibility with +3.3V or
+5V referenced systems. Control inputs are provided for
interleaving additional MAX106 devices to increase the
effective system sampling rate.
The MAX106 is packaged in a 25mm x 25mm, 192-con-
tact Enhanced Super-Ball-Grid Array (ESBGA™), and is
specified over the commercial (0°C to +70°C) temperature
range. For a pin-compatible higher speed upgrade, refer
to the MAX104 (1Gsps) and MAX108 (1.5Gsps) data
sheets.
Applications
Digital RF/IF Signal Processing
Direct RF Downconversion
High-Speed Data Acquisition
Digital Oscilloscopes
High-Energy Physics
Radar/ECM Systems
ATE Systems
Features
o 600Msps Conversion Rate
o 2.2GHz Full-Power Analog Input Bandwidth
o 7.6 Effective Bits at fIN = 300MHz
(Nyquist frequency)
o ±0.25LSB INL and DNL
o 50Ω Differential Analog Inputs
o ±250mV Input Signal Range
o On-Chip, +2.5V Precision Bandgap Voltage
Reference
o Latched, Differential PECL Digital Outputs
o Low Error Rate: 10-27 Metastable States
o Selectable 8:16 Demultiplexer
o Internal Demux Reset Input with Reset Output
o 192-Contact ESBGA
o Pin Compatible with Faster MAX104/MAX108
Ordering Information
PART
MAX106CHC
TEMP RANGE
0°C to +70°C
PIN-PACKAGE
192 ESBGA
TOP VIEW
192-Contact ESBGA
Ball Assignment Matrix
MAX106
Typical Operating Circuit appears at end of data sheet.
ESBGA is a trademark of Amkor/Anam.
ESBGA
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
±5V, 600Msps, 8-Bit ADC with On-Chip
2.2GHz Bandwidth Track/Hold Amplifier
AC ELECTRICAL CHARACTERISTICS (continued)
(VCCA = VCCI = VCCD = +5.0V, VEE = -5.0V, VCCO = +3.3V, REFIN connected to REFOUT, fS = 600Msps, fIN at -1dBFS, TA = +25°C,
unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
TIMING CHARACTERISTICS
Maximum Sample Rate
Clock Pulse Width Low
fMAX
tPWL
Figure 17
600 Msps
0.75 ns
Clock Pulse Width High
tPWH Figure 17
0.75 5 ns
Aperture Delay
Aperture Jitter
Reset Input Data Setup Time
(Note 13)
Reset Input Data Hold Time
(Note 13)
tAD Figure 17
tAJ Figure 4
tSU Figure 15
tHD Figure 15
100
< 0.5
0
0
ps
ps
ps
ps
CLK to DREADY Propagation
Delay
DREADY to DATA Propagation
Delay (Note 14)
DATA Rise Time
DATA Fall Time
DREADY Rise Time
DREADY Fall Time
Primary Port Pipeline Delay
Auxiliary Port Pipeline Delay
tPD1 Figure 17
tPD2 Figure 17
tRDATA
tFDATA
tRDREADY
tFDREADY
tPDP
tPDA
20% to 80%, CL = 3pF
20% to 80%, CL = 3pF
20% to 80%, CL = 3pF
20% to 80%, CL = 3pF
Figures 6, 7, and 8
DIV1, DIV2 modes
DIV4 mode
Figures 6, 7, and 8
DIV1, DIV2 modes
DIV4 mode
2.2 ns
-50 150 350 ps
420 ps
360 ps
220 ps
180 ps
7.5 Clock
7.5 Cycles
8.5 Clock
9.5 Cycles
Note 1: Static linearity parameters are computed from a “best-fit” straight line through the code transition points. The full-scale
range (FSR) is defined as 256 · slope of the line.
Note 2: The offset control input is a self-biased voltage divider from the internal +2.5V reference voltage. The nominal open-circuit
voltage is +1.25V. It may be driven from an external potentiometer connected between REFOUT and GNDI.
Note 3: The clock input’s termination voltage can be operated between -2.0V and GNDI. Observe the absolute maximum ratings on
the CLK+ and CLK- inputs.
Note 4: Input logic levels are measured with respect to the VCCO power-supply voltage.
Note 5: All PECL digital outputs are loaded with 50Ω to VCCO - 2.0V. Measurements are made with respect to the VCCO power-
supply voltage.
Note 6: The current in the VCCO power supply does not include the current in the digital output’s emitter followers, which is a func-
tion of the load resistance and the VTT termination voltage.
Note 7: Common-mode rejection ratio is defined as the ratio of the change in the transfer-curve offset voltage to the change in the
common-mode voltage, expressed in dB.
Note 8: Measured with the positive supplies tied to the same potential, VCCA = VCCD = VCCI. VCC varies from +4.75V to +5.25V.
Note 9: VEE varies from -5.25V to -4.75V.
Note 10: Power-supply rejection ratio is defined as the ratio of the change in the transfer-curve offset voltage to the change in power
supply voltage, expressed in dB.
Note 11: Effective number of bits (ENOB) are computed from a curve fit referenced to the theoretical full-scale range.
_______________________________________________________________________________________ 5
5 Page 
±5V, 600Msps, 8-Bit ADC with On-Chip
2.2GHz Bandwidth Track/Hold Amplifier
CONTACT
J1
J17
J18
K17
K18
L1
L17
L18
M17
M18
N17
N18
P1
P2
P17
P18
R1, R2, R3
R19
T1
U10
U11
U12
U13
U14
U15
U16
V10
V11
V12
V13
V14
V15
V16
NAME
VIN-
A3-
A3+
DREADY-
DREADY+
VIN+
P4-
P4+
A4-
A4+
P5-
P5+
CLK-
TESTPOINT
(T.P.)
A5-
A5+
CLKCOM
AUXEN1
CLK+
RSTIN-
RSTOUT-
OR-
A7-
P7-
A6-
P6-
RSTIN+
RSTOUT+
OR+
A7+
P7+
A6+
P6+
Pin Description (continued)
FUNCTION
Differential Input Voltage (-)
Complementary Auxiliary Output Data Bit 3
Auxiliary Output Data Bit 3
Complementary Data-Ready Clock
Data-Ready Clock
Differential Input Voltage (+)
Complementary Primary Output Data Bit 4
Primary Output Data Bit 4
Complementary Auxiliary Output Data Bit 4
Auxiliary Output Data Bit 4
Complementary Primary Output Data Bit 5
Primary Output Data Bit 5
Complementary Sampling Clock Input
This contact must be connected to GNDI.
Complementary Auxiliary Output Data Bit 5
Auxiliary Output Data Bit 5
50Ω Clock Termination Return
Tie to VCCO to power the auxiliary port. Tie to GNDD to power
down.
Sampling Clock Input
Complementary PECL Demux Reset Input
Complementary PECL Reset Output
Complementary PECL Overrange Bit
Complementary Auxiliary Output Data Bit 7 (MSB)
Complementary Primary Output Data Bit 7 (MSB)
Complementary Auxiliary Output Data Bit 6
Complementary Primary Output Data Bit 6
PECL Demux Reset Input
PECL Reset Output
PECL Overrange Bit
Auxiliary Output Data Bit 7 (MSB)
Primary Output Data Bit 7 (MSB)
Auxiliary Output Data Bit 6
Primary Output Data Bit 6
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MAX106.PDF ] | |
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