|
|
PDF MACHLV210-12JC Data sheet ( Hoja de datos )
| Número de pieza | MACHLV210-12JC | |
| Descripción | High Density EE CMOS Programmable Logic | |
| Fabricantes | Lattice | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de MACHLV210-12JC (archivo pdf) en la parte inferior de esta página. Total 29 Páginas | ||
|
No Preview Available !
FINAL
COM’L: -12/15/20 IND: -18/24
MACHLV210-12/15/20
High Density EE CMOS Programmable Logic
Lattice Semiconductor
DISTINCTIVE CHARACTERISTICS
s Low-voltage operation, 3.3-V JEDEC
compatible
— VCC = +3.0 V to +3.6 V
s < 5 mA standby current
s Patented design allows minimal standby
current without speed degradation
s Exclusively designed for 3.3-V applications
s 44 Pins
s 64 Macrocells
s 12 ns tPDCommercial
18 ns tPDIndustrial
GENERAL DESCRIPTION
The MACHLV210 is a member of the high-
performance EE CMOS MACH 2 device family. This
device has approximately six times the logic macrocell
capability of the popular PAL22V10 at an equal speed
with a lower cost per macrocell. It is architecturally
identical to the MACH210, with the addition of I/O
pull-up/pull-down resistors and low-voltage, low-power
operation.
The MACHLV210 provides 3.3-V operation with low-
power CMOS technology. The patented design
allows for minimal standby current without speed
degradation by limiting the leakage current when
signals are not switching. At less than 5 mA maximum
standby current, the MACHLV210 is ideal for low-power
applications.
The MACHLV210 consists of four PAL blocks intercon-
nected by a programmable switch matrix. The four PAL
blocks are essentially “PAL22V16” structures complete
with product-term arrays and programmable macro-
cells, including additional buried macrocells. The switch
s 83.3 MHz fCNT
s 38 Bus-Friendly Inputs
s 32 Outputs
s 64 Flip-flops; 2 clock choices
s 4 “PAL22V16” blocks with buried macrocells
s Pin-, function-, and JEDEC-compatible with
MACH210
s Pin-compatible with MACH110, MACH111,
MACH210, MACH211, and MACH215
matrix connects the PAL blocks to each other and to all
input pins, providing a high degree of connectivity
between the fully-connected PAL blocks. This allows
designs to be placed and routed efficiently.
The MACHLV210 has two kinds of macrocell: output
and buried. The MACHLV210 output macrocell pro-
vides registered, latched, or combinatorial outputs with
programmable polarity. If a registered configuration is
chosen, the register can be configured as D-type or
T-type to help reduce the number of product terms. The
register type decision can be made by the designer or by
the software. All output macrocells can be connected to
an I/O cell. If a buried macrocell is desired, the internal
feedback path from the macrocell can be used, which
frees up the I/O pin for use as an input.
The MACHLV210 has dedicated buried macrocells
which, in addition to the capabilities of the output
macrocell, also provide input registers or latches for
use in synchronizing signals and reducing setup time
requirements.
Publication# 17908 Rev. D Amendment /0
Issue Date: May 1995
1 page  
ORDERING INFORMATION
Industrial Products
Programmable logic products for industrial applications are available with several ordering options. The order number (Valid
Combination) is formed by a combination of:
MACH LV 210 -18 J I
FAMILY TYPE
MACH = Macro Array CMOS High-Speed
TECHNOLOGY
LV = Low Voltage
DEVICE NUMBER
210 = 64 Macrocells, 44 Pins, Input Pull-Up/Pull-Down
Resistors
SPEED
-18 = 18 ns tPD
-24 = 24 ns tPD
OPTIONAL PROCESSING
Blank = Standard Processing
OPERATING CONDITIONS
I = Industrial (–40°C to +85°C)
PACKAGE TYPE
J = 44-Pin Plastic Leaded Chip
Carrier (PL 044)
Valid Combinations
MACHLV210-18
MACHLV210-24
JI
Valid Combinations
Valid Combinations list configurations planned to be
supported in volume for this device. Consult your local
sales office to confirm availability of specific
valid combinations and to check on newly released
combinations.
MACHLV210-18/24 (Ind)
5
5 Page 
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
(continued)
Parameter
Symbol
Parameter Description
-12
Min Max
tWIGL Input Latch Gate Width LOW
tPDLL Input, I/O, or Feedback to Output Through Transparent
Input and Output Latches
5
17
tAR Asynchronous Reset to Registered or Latched Output
tARW Asynchronous Reset Width (Note 1)
tARR Asynchronous Reset Recovery Time (Note 1)
tAP Asynchronous Preset to Registered or Latched Output
tAPW Asynchronous Preset Width (Note 1)
tAPR Asynchronous Preset Recovery Time (Note 1)
tEA Input, I/O, or Feedback to Output Enable
tER Input, I/O, or Feedback to Output Disable
16
12
12
16
12
12
12
12
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
2. See Switching Test Circuit, for test conditions.
MACHLV210-12 (Com’l)
11
11 Page | ||
| Páginas | Total 29 Páginas | |
| PDF Descargar | [ Datasheet MACHLV210-12JC.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| MACHLV210-12JC | High Density EE CMOS Programmable Logic | Lattice |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |