PDF MACH5 Data sheet ( Hoja de datos )

Número de pieza	MACH5
Descripción	Fifth Generation MACH Architecture
Fabricantes	Lattice
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MACH 5 CPLD Family Fifth Generation MACH Architecture FEATURES x High logic densities and I/Os for increased logic integration — 128 to 512 macrocell densities — 68 to 256 I/Os x Wide selection of density and I/O combinations to support most application needs — 6 macrocell density options — 7 I/O options — Up to 4 I/O options per macrocell density — Up to 5 density & I/O options for each package x Performance features to ﬁt system needs — 5.5 ns tPD Commercial, 7.5 ns tPD Industrial — 182 MHz fCNT — Four programmable power/speed settings per block x Flexible architecture facilitates logic design — Multiple levels of switch matrices allow for performance-based routing — 100% routability and pin-out retention — Synchronous and asynchronous clocking, including dual-edge clocking — Asynchronous product- or sum-term set or reset — 16 to 64 output enables — Functions of up to 32 product terms x Advanced capabilities for easy system integration — 3.3-V & 5-V JEDEC-compliant operations — IEEE 1149.1 compliant for boundary scan testing — 3.3-V & 5-V in-system programmable via IEEE 1149.1 Boundary Scan Test Access Port — PCI compliant (-5/-6/-7/-10/-12 speed grades) — Safe for mixed supply voltage system design — Bus-Friendly™ Inputs & I/Os — Individual output slew rate control — Hot socketing — Programmable security bit x Advanced E2CMOS process provides high performance, cost effective solutions x Supported by ispDesignEXPERT™ software for rapid logic development — Supports HDL design methodologies with results optimized for MACH 5 devices — Flexibility to adapt to user requirements — Software partnerships that ensure customer success x Lattice and Third-party hardware programming support — LatticePRO™ software for in-system programmability support on PCs and Automated Test Equipment — Programming support on all major programmers including Data I/O, BP Microsystems, Advin, and System General Publication# 20446 Rev: I Amendment/0 Issue Date: September 2000 1 page OE Generator Control Generator 32 Block Feeder 32 Product-term Array 2 16 32 Input Register Path 2 Interconnect Feeder Figure 2. PAL Block Structure 20446G-002 Product-Term Array and Logic Allocator The product-term array uses the same sum-of-products architecture as PAL devices and consists of 32 inputs (plus their complements) and 64 product terms arranged in 16 clusters. A cluster is a sum- of-products function with either 3 of 4 product terms. Logic allocators assign the clusters to macrocells. Each macrocell can accept up to eight clusters of three or four product terms, but a given cluster can only be steered to one macrocell (Table 4). If only three product terms in a cluster are steered, the fourth can be used as an input to an XOR gate for separate logic generation and/or polarity control. The wide logic allocator is comprised of all 16 of the individual logic allocators and acts as an output switch matrix by reassigning logic to macrocells to retain pinout as designs change. The logic allocation scheme in the MACH 5 device allows for the implementation of large equations (up to 32 product terms) with only one pass through the logic array. Macrocell M0 M1 M2 M3 M4 M5 M6 M7 Table 4. Product Term Steering Options for PT Clusters and Macrocells Available Clusters Macrocell Available Clusters C0, C1, C2, C3, C4 C0, C1, C2, C3, C4, C5 C0, C1, C2, C3, C4, C5, C6 C0, C1, C2, C3, C4, C5, C6, C7 C0, C1, C2, C3, C4, C5, C6, C7 C1, C2, C3, C4, C5, C6, C7, C8 C2, C3, C4, C5, C6, C7, C8, C9 C3, C4, C5, C6, C7, C8, C9, C10 M8 C5, C6, C7, C8, C9, C10, C11, C12 M9 C6, C7, C8, C9, C10, C11, C12, C13 M10 C7, C8, C9, C10, C11, C12, C13, C14 M11 C8, C9, C10, C11, C12, C13, C14, C15 M12 C8, C9, C10, C11, C12, C13, C14, C15 M13 C9, C10, C11, C12, C13, C14, C15 M14 C10, C11, C12, C13, C14, C15 M15 C11, C12, C13, C14, C15 MACH 5 Family 5 5 Page SAFE FOR MIXED SUPPLY VOLTAGE SYSTEM DESIGNS 1 Both the 3.3-V and 5-V VCC MACH 5 devices are safe for mixed supply voltage system designs. The 5-V devices will not overdrive 3.3-V devices above the output voltage of 3.3 V, while they accept inputs from other 3.3-V devices. The 3.3-V devices will accept inputs up to 5.5 V. Both the 3.3-V and 5-V versions have the same high-speed performance and provide easy-to-use mixed- voltage design capability. Note: 1. Excludes original M5-128, M5-192, and M5-256 while M5-128/1, M3-192/1 and M5-256/1 are supported. Please refer to Application Note titled “Hot Socketing and Mixed Supply Design with MACH 4 and MACH 5 Devices”. BUS-FRIENDLY INPUTS AND I/OS All MACH 5 devices have inputs and I/Os which feature the Bus-Friendly circuitry incorporating two inverters in series which loop back to the input. This double inversion weakly holds the input at its last driven logic state. While it is a good design practice to tie unused pins to a known state, the Bus-Friendly input structure pulls pins away from the input threshold voltage where noise can cause high-frequency switching. At power-up, the Bus-Friendly latches are reset to a logic level “1.” For the circuit diagram, please refer to the document entitled MACH Endurance Characteristics on the Lattice Data Book CD-ROM or Lattice web site. POWER MANAGEMENT There are 4 power/speed options in each MACH 5 PAL block (Table 5). The speed and power tradeoff can be tailored for each design. The signal speed paths in the lower-power PAL blocks will be slower than those in the higher-power PAL blocks. This feature allows speed critical paths to run at maximum frequency while the rest of the signal paths operate in a lower-power mode. In large designs, there may be several different speed requirements for different portions of the design. Table 5. Power Levels High Speed/High Power 100% Power Medium High Speed/Medium High Power 67% Power Medium Low Speed/Medium Low Power 40% Power Low Speed/Low Power 20% Power PROGRAMMABLE SLEW RATE Each MACH 5 device I/O has an individually programmable output slew rate control bit. Each output can be individually conﬁgured for the higher speed transition (3 V/ns) or for the lower noise transition (1 V/ns). For high-speed designs with long, unterminated traces, the slow-slew rate will introduce fewer reﬂections, less noise, and keep ground bounce to a minimum. For designs with short traces or well terminated lines, the fast slew rate can be used to achieve the highest speed. The slew rate is adjusted independent of power. POWER-UP RESET/SET All ﬂip-ﬂops power up to a known state for predictable system initialization. If a macrocell is conﬁgured to SET on a signal from the control generator, then that macrocell will be SET during device power-up. If a macrocell is conﬁgured to RESET on a signal from the control generator or is not conﬁgured for set/reset, then that macrocell will RESET on power-up. To guarantee MACH 5 Family 11 11 Page

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