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PDF MACH230-20JC Data sheet ( Hoja de datos )
| Número de pieza | MACH230-20JC | |
| Descripción | High-Density EE CMOS Programmable Logic | |
| Fabricantes | Lattice | |
| Logotipo |  |
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FINAL
COM’L: -10/15/20 IND: -18/24
MACH230-10/15/20
High-Density EE CMOS Programmable Logic
Lattice Semiconductor
DISTINCTIVE CHARACTERISTICS
84 Pins
128 Macrocells
10 ns tPD Commercial
18 ns tPD Industrial
100 MHz fCNT
70 Inputs
GENERAL DESCRIPTION
The MACH230 is a member of the high-performance
EE CMOS MACH 2 device family. This device has ap-
proximately twelve times the logic macrocell capability
of the popular PAL22V10 without loss of speed.
The MACH230 consists of eight PAL blocks intercon-
nected by a programmable switch matrix. The switch
matrix connects the PAL blocks to each other and to all
input pins, providing a high degree of connectivity be-
tween the fully-connected PAL blocks. This allows
designs to be placed and routed efficiently.
The MACH230 has two kinds of macrocell: output and
buried. The output macrocell provides registered,
BLOCK DIAGRAM
If you would like to view
Block Diagram in full size,
please click on the box.
64 Outputs
128 Flip-flops; 4 clock choices
8 “PAL26V16” blocks with buried macrocells
Pin-compatible with MACH130, MACH131,
MACH231, and MACH435
latched, or combinatorial outputs with programmable
polarity. If a registered configuration is chosen, the reg-
ister can be configured as D-type or T-type to help
reduce the number of product terms. The register type
decision can be made by the designer or by the soft-
ware. All output macrocells can be connected to an I/O
cell. If a buried macrocell is desired, the internal feed-
back path from the macrocell can be used, which frees
up the I/O pin for use as an input.
The MACH230 has dedicated buried macrocells which,
in addition to the capabilities of the output macrocell,
also provide input registers for use in synchronizing
signals and reducing setup time requirements.
Publication# 14132 Rev. I Amendment /0
Issue Date: May 1995
1 page  
ORDERING INFORMATION
Industrial Products
Programmable logic products for industrial applications are available with several ordering options. The order number (Valid
Combination) is formed by a combination of:
MACH 230 -18 J I
FAMILY TYPE
MACH = Macro Array CMOS High-Speed
DEVICE NUMBER
230 = 128 Macrocells, 84 Pins
SPEED
-18 = 18 ns tPD
-24 = 24 ns tPD
OPTIONAL PROCESSING
Blank = Standard Processing
OPERATING CONDITIONS
I = Industrial (–40°C to +85°C)
PACKAGE TYPE
J = 84-Pin Plastic Leaded
Chip Carrier (PL 084)
Valid Combinations
MACH230-18
MACH230-24
JI
Valid Combinations
The Valid Combinations table lists configurations
planned to be supported in volume for this device.
Consult your local sales office to confirm availabil-
ity of specific valid combinations and to check on newly
released combinations.
MACH230-18/24 (Ind)
5
5 Page 
ABSOLUTE MAXIMUM RATINGS
Storage Temperature . . . . . . . . . . . –65°C to +150°C
Ambient Temperature
With Power Applied . . . . . . . . . . . . . –55°C to +125°C
Supply Voltage with
Respect to Ground . . . . . . . . . . . . . –0.5 V to +7.0 V
DC Input Voltage . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
DC Output or I/O
Pin Voltage . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Static Discharge Voltage . . . . . . . . . . . . . . . . 2001 V
Latchup Current
(TA = 0°C to 70°C) . . . . . . . . . . . . . . . . . . . . . 200 mA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum
Ratings for extended periods may affect device reliability. Pro-
gramming conditions may differ.
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (TA)
Operating in Free Air . . . . . . . . . . . . . . 0°C to +70°C
Supply Voltage (VCC)
with Respect to Ground . . . . . . . . +4.75 V to +5.25 V
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter
Symbol
Parameter Description
Test Conditions
Min Typ Max Unit
VOH Output HIGH Voltage
IOH = –3.2 mA, VCC = Min
VIN = VIH or VIL
2.4
V
VOL Output LOW Voltage
IOL = 16 mA, VCC = Min
VIN = VIH or VIL
0.5 V
VIH Input HIGH Voltage
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1)
2.0
V
VIL Input LOW Voltage
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)
0.8 V
IIH Input HIGH Current
VIN = 5.25 V, VCC = Max (Note 2)
10 µA
IIL Input LOW Current
VIN = 0 V, VCC = Max (Note 2)
–10 µA
IOZH Off-State Output Leakage VOUT = 5.25 V, VCC = Max
Current HIGH
VIN = VIH or VIL (Note 2)
10 µA
IOZL Off-State Output Leakage VOUT = 0 V, VCC = Max
Current LOW
VIN = VIH or VIL (Note 2)
–10 µA
ISC
Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3)
–30
–130 mA
ICC Supply Current (Typical)
VCC = 5 V, TA = 25°C, f = 25 MHz
(Note 4)
235 mA
Notes:
1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included.
2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH).
3. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
4. Measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and is capable of being
loaded, enabled, and reset.
MACH230-15/20 (Com’l)
11
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