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MACH130-20JC fiches techniques PDF

Lattice - High-Density EE CMOS Programmable Logic

Numéro de référence MACH130-20JC
Description High-Density EE CMOS Programmable Logic
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MACH130-20JC fiche technique
FINAL
COM’L: -15/20
IND: -18/24
MACH130-15/20
High-Density EE CMOS Programmable Logic
Lattice Semiconductor
DISTINCTIVE CHARACTERISTICS
84 Pins
64 Macrocells
15 ns tPD Commercial
18 ns tPD Industrial
66.6 MHz fCNT
70 Inputs
GENERAL DESCRIPTION
The MACH130 is a member of the high-performance
EE CMOS MACH 1 family. This device has approxi-
mately six times the logic macrocell capability of the
popular PAL22V10 without loss of speed.
The MACH130 consists of four PAL blocks intercon-
nected by a programmable switch matrix. The switch
matrix connects the PAL blocks to each other and to all
input pins, providing a high degree of connectivity
between the fully-connected PAL blocks. This allows
designs to be placed and routed efficiently.
64 Outputs
64 Flip-flops; 4 clock choices
4 “PAL26V16” Blocks
Pin-compatible with MACH131, MACH230,
MACH231, MACH435
The MACH130 macrocell provides either registered or
combinatorial outputs with programmable polarity. If a
registered configuration is chosen, the register can be
configured as D-type or T-type to help reduce the
number of product terms. The register type decision can
be made by the designer or by the software. All
macrocells can be connected to an I/O cell. If a buried
macrocell is desired, the internal feedback path from the
macrocell can be used, which frees up the I/O pin for use
as an input.
Publication# 14131 Rev. H Amendment /0
Issue Date: April 1995

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