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MACH120-12JC fiches techniques PDF

Lattice - High-Performance EE CMOS Programmable Logic

Numéro de référence MACH120-12JC
Description High-Performance EE CMOS Programmable Logic
Fabricant Lattice 
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MACH120-12JC fiche technique
Lattice Semiconductor
1
FINAL
COM’L: -12/15
MACH 1 & 2 FAMILIES
IND: -18
MACH120-12/15
High-Performance EE CMOS Programmable Logic
DISTINCTIVE CHARACTERISTICS
x 68 Pins in PLCC
x 48 Macrocells
x 12 ns tPD Commercial, 18 ns tPD Industrial
x 77 MHz fCNT Commercial
x 48 I/Os; 4 dedicated inputs; 4 dedicated inputs/clocks
x 48 Outputs
x 48 Flip-flops; 4 clock choices
x 4 “PALCE26V12” blocks
x SpeedLocking™ for guaranteed fixed timing
x Pin-compatible with the MACH221
GENERAL DESCRIPTION
The MACH120 is a member of the high-performance EE CMOS MACH ® 1 family. This device
has approximately five times the logic macrocell capability of the popular PALCE22V10 without
loss of speed.
The MACH120 consists of four PAL® blocks interconnected by a programmable switch matrix.
The switch matrix connects the PAL blocks to each other and to all input pins, providing a high
degree of connectivity between the fully-connected PAL blocks. This allows designs to be placed
and routed efficiently.
The MACH120 macrocell provides either registered or combinatorial outputs with programmable
polarity. If a registered configuration is chosen, the register can be configured as D-type or T-type
to help reduce the number of product terms. The register type decision can be made by the
designer or by the software. All macrocells can be connected to an I/O cell. If a buried macrocell
is desired, the internal feedback path from the macrocell can be used, which frees up the I/O pin
for use as an input.
Publication# 14129 Rev: J
Amendment/0
Issue Date: November 1997

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