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Motorola Semiconductors - MAC7100 Microcontroller Family Hardware Specifications

Numéro de référence MAC7121VPV
Description MAC7100 Microcontroller Family Hardware Specifications
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Advance Information
Freescale Semiconductor, Inc.
MAC7100EC/D
Rev. 0.1, 10/2003
MAC7100 Microcontroller
Family Hardware
Specifications
32-bit Embedded
Controller Division
This document provides electrical specifications, pin assignments, and package diagrams for
MAC7100 family of microcontroller devices. For functional characteristics of the family,
refer to the MAC7100 Microcontroller Family Reference Manual (MAC7100RM/D).
This document contains the following topics:
Topic
Page
Section 1, “Overview”
1
Section 2, “Ordering Information”
2
Section 3, “Electrical Characteristics”
3
Section 4, “Device Pin Assignments”
36
Section 5, “Mechanical Information”
41
1 Overview
The MAC7100 Family of microcontrollers (MCUs) are members of a pin-compatible family
of 32-bit Flash-memory-based devices developed specifically for embedded automotive
applications. The pin-compatible family concept enables users to select between different
memory and peripheral options for scalable designs. All MAC7100 Family members are
composed of a 32-bit central processing unit (ARM7TDMI-S), up to 512Kbytes of embedded
Flash EEPROM for program storage, up to 32Kbytes of embedded Flash for data and/or
program storage, and up to 32Kbytes of RAM. The family is implemented with an enhanced
DMA (eDMA) controller to improve performance for transfers between memory and many of
the on-chip peripherals. The peripheral set includes asynchronous serial communications
interfaces (eSCI), serial peripheral interfaces (DSPI), inter-integrated circuit (I2C) bus
controllers, FlexCAN interfaces, an enhanced modular I/O subsystem (eMIOS), 10-bit
analog-to-digital converter (ATD) channels, general-purpose timers (PIT) and two
special-purpose timers (RTI and SWT). The peripherals share a large number of general
purpose input-output (GPIO) pins, all of which are bidirectional and available with interrupt
capability to trigger wake-up from low-power chip modes.
The inclusion of a PLL circuit allows power consumption and performance to be adjusted to
suit operational requirements. The operating frequency of devices in the family is up to a
maximum of 50 MHz. The internal data paths between the CPU core, eDMA, memory and
peripherals are all 32 bits wide, further improving performance for 32-bit applications. The
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
For More Information On This Product,
Go to: www.freescale.com

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