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PDF MA31755 Data sheet ( Hoja de datos )
| Número de pieza | MA31755 | |
| Descripción | 16-Bit Feedthrough Error Detection & Correction Unit EDAC | |
| Fabricantes | Dynex | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MA31755 (archivo pdf) en la parte inferior de esta página. Total 13 Páginas | ||
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Replaces June 1999 version, DS3572-3.0
MAM3A137175555
16-Bit Feedthrough Error Detection
& Correction Unit (EDAC)
DS3572-4.0 January 2000
The MA31755 is a 16 bit Error Detection and Correction
Unit intended for use in high integrity systems for monitoring
and correcting data values retrieved from memory. The EDAC
is placed in the data bus between the processor and the
memory to be protected. Extra check bits added at each
memory location are programmed transparently by the EDAC
during a processor write cycle. The entire checkword and data
combination is verified on read cycles. If any one bit in the
incoming data stream is at fault the EDAC can correct the fault
transparently, presenting the corrected 16-bit value to the
processor. An error in two bits can be detected but cannot be
corrected. Both the correctable and uncorrectable error
conditions are signalled to the system to allow the processor to
take action as required. Parity is passed through the device
unchanged as data bus bit 16.
Tri-statable bus transceivers with a high drive capability
are incorporated at the MD and CB busses which allows the
usual bus driver devices to be removed and reduces the
overall timing overhead imposed on the data bus. Although
designed primarily for MA31750 application, this part may be
used in almost any 16-bit processor system requiring high data
integrity.
FEATURES
s Fast Feedthrough (35ns Detect and Correct Cycle)
s 16-Bit Operation with 6 Check Bits
s Radiation Hard CMOS/SOS Technology
s Feedthrough Operation
s Error Corrected/Uncorrected Flags
s High Drive Capability on Memory Busses
8
VDD
8
VSS
MD[0:16]
CB[0:5]
MA31755
EDAC
PD[0:16]
CERRN
NCERRN
RDWN
XERRN
ENCOR
ENFLG
CS0
CS1N
CS2N
Figure 1: Chip Signals
1/13
1 page  
3. TIMING DIAGRAMS
MA31755
PD[0:16] Data from processor
MD[0:16]
CB[0:5]
CERRN
NCERRN
CS0
CS1N
CS2N
RDWN
T6
T9
Data and check bits to memory
T1
T4
Valid Flags
T8
T10
Figure 6 : Processor Write Timings (ENFLG = 1)
CB[0:5] Check bits from memory
MD[0:16] Data from memory
PD[0:16]
CERRN
NCERRN
RDWN
CS0
CS1N
CS2N
T6
T5
T3
T2
T4
Valid Data
Valid Flags
T8
T7
Figure 7: Processor Read Timings (ENCOR and ENFLG=1)
5/13
5 Page 
MA31755
VDD
ENCOR
ENFLG
CS2N
CS1N
CS0
PD0
GND
VDD
PD1
PD2
PD3
PD4
PD5
PD6
PD7
GND
26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
27 9
28 8
29 7
30 6
31 5
32 4
33 3
34
35
TOP VIEW
Pin 1
Index
2
1
36 68
37 67
38 66
39 65
40 64
41 63
42 62
43 61
44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
GND
MD12
MD13
MD14
MD15
MD16
NC
VDD
GND
NC
CB0
CB1
CB2
CB3
CB4
CB5
VDD
Figure 18: Pinout for the 68-pin Flatpack Package
11/13
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet MA31755.PDF ] | |
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