PDF IDT5V9950PFI Data sheet ( Hoja de datos )

Número de pieza	IDT5V9950PFI
Descripción	3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
Fabricantes	Integrated Device
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No Preview Available ! IDT5V9950 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR. 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK™ II JR. INDUSTRIALTEMPERATURERANGE IDT5V9950 FEATURES: • Ref input is 5V tolerant • 4 pairs of programmable skew outputs • Low skew: 185ps same pair, 250ps all outputs • Selectable positive or negative edge synchronization: Excellent for DSP applications • Synchronous output enable • Input frequency: 6MHz to 200MHz • Output frequency: 6MHz to 200MHz • 2x, 4x, 1/2, and 1/4 outputs • 3-level inputs for skew and PLL range control • PLL bypass for DC testing • External feedback, internal loop filter • 12mA balanced drive outputs • Low Jitter: <100ps cycle-to-cycle • Available in TQFP package DESCRIPTION: The IDT5V9950 is a high fanout 3.3V PLL based clock driver intended for high performance computing and data-communications applications. A key feature of the programmable skew is the ability of outputs to lead or lag the REF input signal. The IDT5V9950 has eight programmable skew outputs in four banks of 2. Skew is controlled by 3-level input signals that may be hard-wired to appropriate HIGH-MID-LOW levels. When the sOE pin is held low, all the outputs are synchronously enabled. However, if sOE is held high, all the outputs except 2Q0 and 2Q1 are synchronously disabled. Furthermore, when PE is held high, all the outputs are synchronized with the positive edge of the REF clock input. When PE is held low, all the outputs are synchronized with the negative edge of REF. The IDT5V9950 has LVTTL outputs with 12mA balanced drive outputs. FUNCTIONAL BLOCK DIAGRAM REF FB PE TEST 3 PLL 3 FS The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE c 2002 Integrated Device Technology, Inc. sOE Skew Select 33 1F1:0 Skew Select 33 2F1:0 Skew Select 33 3F1:0 Skew Select 33 4F1:0 1 1Q0 1Q1 2Q0 2Q1 3Q0 3Q1 4Q0 4Q1 FEBRUARY 2002 DSC 5870/4 1 page IDT5V9950 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR. POWER SUPPLY CHARACTERISTICS Symbol Parameter Test Conditions(1) IDDQ Quiescent Power Supply Current VDD = Max., TEST = MID, REF = LOW, PE = LOW, sOE = LOW, FS = MID All outputs unloaded ∆IDD Power Supply Current per Input HIGH VIN = 3V, VDD = Max., TEST = HIGH (REF and FB inputs only) FS = L IDDD Dynamic Power Supply Current per Output FS = M FS = H FS = L , FVCO = 50MHz, CL = 0pF ITOT Total Power Supply Current FS = M , FVCO = 100MHz, CL = 0pF FS = H, FVCO = 200MHz, CL = 0pF NOTES: 1. Measurements are for divide-by-1 outputs and nF[1:0] = MM. 2. For nominal voltage and temperature. INDUSTRIALTEMPERATURERANGE Typ.(2) 20 Max. 30 Unit mA 1 30 µA 190 290 150 230 µA/MHz 130 200 56 — 80 — mA 125 — INPUT TIMING REQUIREMENTS Symbol Description(1) tR, tF Maximum input rise and fall times, 0.8V to 2V tPWC Input clock pulse, HIGH or LOW DH Input duty cycle FREF Referenceclockinputfrequency NOTE: 1. Where pulse width implied by DH is less than tPWC limit, tPWC limit applies. FS = LOW FS = MID FS = HIGH Min. Max. Unit — 10 ns/V 2 — ns 10 90 % 6 50 12 100 MHz 24 200 5 5 Page

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