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PDF IDT5V993-7Q Data sheet ( Hoja de datos )
| Número de pieza | IDT5V993-7Q | |
| Descripción | 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK | |
| Fabricantes | Integrated Device | |
| Logotipo |  |
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IDT5V993A
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
3.3V PROGRAMMABLE
SKEW PLL CLOCK DRIVER
TURBOCLOCK™
IDT5V993A
FEATURES:
• Ref input is 5V tolerant
• 3 pairs of programmable skew outputs
• Low skew: 200ps same pair, 250ps all outputs
• Selectable positive or negative edge synchronization:
Excellent for DSP applications
• Synchronous output enable
• Output frequency: 3.75MHz to 85MHz
• 2x, 4x, 1/2, and 1/4 outputs
• 3 skew grades:
IDT5V993A-2: tSKEW0<250ps
IDT5V993A-5: tSKEW0<500ps
IDT5V993A-7: tSKEW0<750ps
• 3-level inputs for skew and PLL range control
• PLL bypass for DC testing
• External feedback, internal loop filter
• 12mA balanced drive outputs
• Low Jitter: <200ps peak-to-peak
• Available in QSOP package
DESCRIPTION:
The IDT5V993A is a high fanout 3.3V PLL based clock driver intended
for high performance computing and data-communications applications. A
key feature of the programmable skew is the ability of outputs to lead or lag
the REF input signal. The IDT5V993A has six programmable skew outputs
and two zero skew outputs. Skew is controlled by 3-level input signals that
may be hard-wired to appropriate HIGH-MID-LOW levels.
When the GND/sOE pin is held low, all the outputs are synchronously
enabled. However, if GND/sOE is held high, all the outputs except 3Q0 and
3Q1 are synchronously disabled.
Furthermore, when the VCCQ/PE is held high, all the outputs are
synchronized with the positive edge of the REF clock input. When VCCQ/
PE is held low, all the outputs are synchronized with the negative edge of
REF. Both devices have LVTTL outputs with 12mA balanced drive outputs.
FUNCTIONAL BLOCK DIAGRAM
V C CQ /P E
REF
FB
PLL
3
FS
G N D /sO E
Skew
S e le ct
33
1F1:0
Skew
S e le ct
33
2F1:0
Skew
S e le ct
33
3F1:0
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL
c 2001 Integrated Device Technology, Inc.
TEMPERATURE
1
RANGES
1Q0
1Q1
2Q0
2Q1
3Q0
3Q1
4Q0
4Q1
SEPTEMBER 2001
DSC 5408/1
1 page  
IDT5V993A
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
INPUT TIMING REQUIREMENTS
Symbol
Description (1)
tR, tF Maximum input rise and fall times, 0.8V to 2V
tPWC Input clock pulse, HIGH or LOW
DH Input duty cycle
REF Reference Clock Input
NOTE:
1. Where pulse width implied by DH is less than tPWC limit, tPWC limit applies.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
Min. Max. Unit
— 10 ns/V
3 — ns
10 90 %
3.75 85 MHz
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Symbol Parameter
FNOM VCO Frequency Range
tRPWH REF Pulse Width HIGH(11)
tRPWL REF Pulse Width LOW(11)
tU Programmable Skew Time Unit
tSKEWPR Zero Output Matched-Pair Skew (xQ0, xQ1)(1,2,3)
tSKEW0 Zero Output Skew (All Outputs)(1,4)
tSKEW1 Output Skew
(Rise-Rise, Fall-Fall, Same Class Outputs)(1,6)
tSKEW2 Output Skew
(Rise-Fall, Divided-Divided)(1,6)
tSKEW3 Output Skew
(Rise-Rise, Fall-Fall, Different Class Outputs)(1,6)
tSKEW4 Output Skew
(Rise-Fall, Nominal-Divided)(1,2)
tDEV Device-to-Device Skew(1,2,7)
tPD REF Input to FB Propagation Delay(1,9)
tODCV Output Duty Cycle Variation from 50%(1)
tPWH Output HIGH Time Deviation from 50%(1,10)
tPWL Output LOW Time Deviation from 50%(1,11)
tORISE Output Rise Time(1)
tOFALL Output Fall Time(1)
tLOCK PLL Lock Time(1,8)
tJR Cycle-to-Cycle Output Jitter(1) RMS
Peak-to-Peak
IDT5V993A-2
IDT5V993A-5
IDT5V993A-7
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
See PLL Programmable Skew Range and Resolution Table
3— —
3 — — 3 ——
3— —
3 — — 3 ——
See Control Summary Table
— 0.05 0.2
— 0.1 0.25 — 0.1 0.25
— 0.1 0.25 — 0.25 0.5 — 0.3 0.75
— 0.25 0.5
— 0.6
0.7 — 0.6
1
Unit
ns
ns
ns
ns
ns
— 0.3 1.2 — 0.5 1.2 — 1 1.5 ns
— 0.25 0.5
— 0.5 0.7 — 0.7 1.2 ns
— 0.5 0.9 — 0.5 1 — 1.2 1.7 ns
—
−0.25
−1.2
—
—
0.15
0.15
—
—
—
—
0
0
—
—
1
1
—
—
—
0.75 — —
0.25 −0.5 0
1.2 −1.2 0
1.25 —
— 1.65 ns
0.5 −0.7 0
0.7 ns
1.2 −1.2 0
1.2 ns
2
——
2.5 — —
3 ns
1.5 — — 3 — — 3.5 ns
1.2 0.15 1
1.8 0.15 1.5 2.5 ns
1.2 0.15 1
1.8 0.15 1.5 2.5 ns
0.5
——
0.5 — — 0.5 ms
25
——
25 — — 25 ps
200 — — 200 — — 200
NOTES:
1. All timing and jitter tolerances apply for FNOM > 25MHz.
2. Skew is the time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with the specified
load.
3. tSKEWPR is the skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0tU.
4. tSKEW0 is the skew between outputs when they are selected for 0tU.
5. For IDT5V993A-2 tSKEW0 is measured with CL = 0pF; for CL = 20pF, tSKEW0 = 0.35ns Max.
6. There are 2 classes of outputs: Nominal (multiple of tU delay), and Divided (3Qx only in Divide-by-2 or Divide-by-4 mode).
7. tDEV is the output-to-output skew between any two devices operating under the same conditions (VCC, ambient temperature, air flow, etc.)
8. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter is
measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
9. tPD is measured with REF input rise and fall times (from 0.8V to 2V) of 1ns.
10. Measured at 2V.
11. Measured at 0.8V.
5
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