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IDT5T940-30NLI fiches techniques PDF

Integrated Device - PRECISION CLOCK GENERATOR OC-192 APPLICATIONS

Numéro de référence IDT5T940-30NLI
Description PRECISION CLOCK GENERATOR OC-192 APPLICATIONS
Fabricant Integrated Device 
Logo Integrated Device 





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IDT5T940-30NLI fiche technique
IDT5T940
PRECISION CLOCK GENERATOR OC-192 APPLICATIONS
INDUSTRIALTEMPERATURERANGE
PRECISION CLOCK GENERATOR
OC-192 APPLICATIONS
IDT5T940
FEATURES:
• Input frequency:
- For SONET non-FEC: 19.44MHz, 38.88MHz, 77.76MHz, 155.52MHz,
311.04MHz, or 622.08MHz
- For SONET FEC: 20.83MHz, 41.66MHz, 83.31MHz, 166.63MHz,
333.26MHz, or 666.52MHz
- For 10GE copper: 19.53MHz, 39.06MHz, 78.125MHz, 156.25MHz,
312.5MHz, or 625MHz
- For 10GE optical: 20.14MHz, 40.28MHz, 80.56MHz, 161.13MHz,
322.26MHz, or 644.53MHz
• 3-level inputs for feedback divide ratio and output frequency range
selection
• 1x, 2x, 4x, 8x, 16x, and 32x outputs on QOUT
• Regenerated input clock or QOUT/4 on QREG
• Lock indicator
• Power-down mode
• LVPECL or LVDS outputs
• Three modes of output frequency range
- Mode 0: QOUT range 155.5 - 166.6MHz. QREG is a regenerated version
of the input clock.
- Mode 1: QOUT range 622 - 666.5MHz. QREG output 155.5-166.6MHz.
- Mode 2: QOUT range 622 - 666.5MHz. QREG is a regenerated version
of the input clock frequency.
• Selectable loop bandwidths
• Hitless switchover
• Differential LVPECL, LVDS, or single-ended LVTTL input interface
• 2.375 - 3.465V core and I/O
• Available in VFQFPN package
DESCRIPTION:
The IDT5T940 generates a high precision FEC (Forward Error Cor-
rection) or non-FEC source clock for SONET/SDH systems as well as a
source clock for Gigabit Ethernet systems. This device also has clock
regeneration capability: it creates a "clean" version of the clock input by
using the internal oscillator to square the input clock's rising and falling
edges and remove jitter. In the event that the main clock input fails, the
device automatically locks to a backup reference clock using a hitless
switchover mechanism.
This device detects loss of valid CLKIN and leaves the VCO of the PLL at
the last valid frequency while an alternate input REFIN is selected. If CLKIN
and REFIN are different frequencies, the multiplication factor will be adjusted to
retain the same output frequency.
The IDT5T940 can act as a translator from a differential LVPECL, LVDS, or
single-ended LVTTL input to LVPECL or LVDS outputs. The IDT5T940-10
has LVDS outputs and the IDT5T940-30 has LVPECL outputs.
The three modes of output frequency range are controlled by the SELmode,
which is a 3-level pin. When SELmode is high or low, the QOUT is a multiplied
version of the input clock while QREG is a regenerated version of the input clock.
When SELmode is mid, the QOUT is a multiplied version of the input clock while
QREG is QOUT/4.
The IDT5T940 features a selectable loop bandwidth.
APPLICATIONS:
• Terabit routers
• Gigabit ethernet systems
• SONET / SDH systems
• Digital cross connects
• Optical transceiver modules
FUNCTIONAL BLOCK DIAGRAM
CLKIN
CLKIN
INPUT
MUX
PLLBW1 PLLBW0
PLL
DIVN
QREG
QREG
REFIN
REFIN
LOCK
LOCK,
FREQ.
DETECTOR
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
c 2003 Integrated Device Technology, Inc.
CONTROL
LOGIC
PD
SELMODE
CLK/
REF0
CLK/
REF1
1
DIVM
QOUT
QOUT
DECEMBER 2003
DSC 6195/23

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