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Integrated Device - HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS

Numéro de référence IDT54FCT823ATD
Description HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
Fabricant Integrated Device 
Logo Integrated Device 





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IDT54FCT823ATD fiche technique
IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
HIGH-PERFORMANCE
IDT54/74FCT821AT/BT/CT
CMOS BUS
INTERFACE REGISTERS
IDT54/74FCT823AT/BT/CT/DT
IDT54/74FCT825AT/BT/CT
Integrated Device Technology, Inc.
FEATURES:
• Common features:
– Low input and output leakage 1µA (max.)
– CMOS power levels
– True TTL input and output compatibility
– VOH = 3.3V (typ.)
– VOL = 0.3V (typ.)
– Meets or exceeds JEDEC standard 18 specifications
– Product available in Radiation Tolerant and Radiation
Enhanced versions
– Military product compliant to MIL-STD-883, Class B
and DESC listed (dual marked)
– Available in DIP, SOIC, SSOP, QSOP, CERPACK
and LCC packages
• Features for FCT821T/FCT823T/FCT825T:
– A, B, C and D speed grades
– High drive outputs (-15mA IOH, 48mA IOL)
– Power off disable outputs permit “live insertion”
DESCRIPTION:
The FCT82xT series is built using an advanced dual metal
CMOS technology. The FCT82xT series bus interface regis-
ters are designed to eliminate the extra packages required to
buffer existing registers and provide extra data width for wider
address/data paths or buses carrying parity. The FCT821T
are buffered, 10-bit wide versions of the popular FCT374T
function. The FCT823T are 9-bit wide buffered registers with
Clock Enable (EN) and Clear (CLR) – ideal for parity bus
interfacing in high-performance microprogrammed systems.
The FCT825T are 8-bit buffered registers with all the FCT823T
controls plus multiple enables (OE1, OE2, OE3) to allow multi-
user control of the interface, e.g., CS, DMA and RD/WR. They
are ideal for use as an output port requiring high IOL/IOH.
The FCT82xT high-performance interface family can drive
large capacitive loads, while providing low-capacitance bus
loading at both inputs and outputs. All inputs have clamp
diodes and all outputs are designed for low-capacitance bus
loading in high-impedance state.
FUNCTIONAL BLOCK DIAGRAM
D0
EN
DN
CLR
CP
D CL Q
CP Q
D CL Q
CP Q
OE
Y0
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1995 Integrated Device Technology, Inc
66..2211
YN
2567 drw 01
AUGUST 1995
DSC-42102/5
1

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