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PDF IDT54FCT139 Data sheet ( Hoja de datos )
| Número de pieza | IDT54FCT139 | |
| Descripción | FAST CMOS DUAL 1-OF-4 DECODER WITH ENABLE | |
| Fabricantes | Integrated Device | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de IDT54FCT139 (archivo pdf) en la parte inferior de esta página. Total 6 Páginas | ||
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IDT54/74FCT139/A/C
FAST CMOS DUAL 1-0F-4®DECODER WITH ENABLE
FAST CMOS DUAL
1-OF-4 DECODER
Integrated Device Technology, Inc.
WITH ENABLE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT54/74FCT139
IDT54/74FCT139A
IDT54/74FCT139C
FEATURES:
• IDT54/74FCT139 equivalent to FAST™ speed
• IDT54/74FCT139A 35% faster than FAST
• IDT54/74FCT139C 45% faster than FAST
• Equivalent to FAST output drive over full temperature
and voltage supply extremes
• IOL = 48mA (commercial) and 32mA (military)
• CMOS power levels (1mW typ. static)
• TTL input and output level compatible
• CMOS output level compatible
• Substantially lower input current levels than FAST
(5µA max.)
• JEDEC standard pinout for DIP and LCC
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The IDT54/74FCT139/A/C are dual 1-of-4 decoders built
using an advanced dual metal CMOS technology. These
devices have two independent decoders, each of which
accept two binary weighted inputs (A0-A1) and provide four
mutually exclusive active LOW outputs (O0-O3). Each de-
coder has an active LOW enable (E). When E is HIGH, all
outputs are forced HIGH.
FUNCTIONAL BLOCK DIAGRAM
Ea
A0a A1a
Eb
PIN CONFIGURATIONS
A0b A1b
Ea
A0a
A1a
O0a
O1a
O2a
O3a
GND
1 16
2
15
P16-1
3 D16-1 14
4 SO16-1 13
5 & 12
6 E16-1 11
7 10
89
VCC
Eb
A0b
A1b
O0b
O1b
O2b
O3b
DIP/SOIC/CERPACK
TOP VIEW
2605 cnv* 01
O0a O1a O2a
O3a O0b O1b O2b
O3b
2605 cnv* 03
INDEX
3 2 20 19
A1a 4
1 18 A0b
O0a 5
17 A1b
NC 6
L20-2 16 NC
O1a 7
15 O0b
O2a 8
14 O1b
9 10 11 12 13
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1992 Integrated Device Technology, Inc.
7.4
7.4
LCC
TOP VIEW
2605 cnv* 02
MAY 1992
DSC 4613/3
11
1 page  
IDT54/74FCT139/A/C
FAST CMOS DUAL 1-0F-4 DECODER WITH ENABLE
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
VCC 7.0V
VIN
Pulse
Generator
V OUT
D.U.T.
500Ω
50pF
500Ω
RT CL
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
All Other Tests
Switch
Closed
Open
DEFINITIONS:
2605 tbl 08
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
ETC.
t SU
t SU
tH
t REM
tH
PULSE WIDTH
3V
1.5V
0V
3V
1.5V
0V
LOW-HIGH-LOW
PULSE
3V
1.5V
0V
HIGH-LOW-HIGH
PULSE
3V
1.5V
0V
1.5V
tW
1.5V
PROPAGATION DELAY
SAME PHASE
INPUT TRANSITION
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
tPLH
t PLH
t PHL
tPHL
3V
1.5V
0V
VOH
1.5V
VOL
3V
1.5V
0V
ENABLE AND DISABLE TIMES
ENABLE
CONTROL
INPUT
OUTPUT
NORMALLY
LOW
t PZL
SWITCH
CLOSED
t PZH
OUTPUT SWITCH
NORMALLY OPEN
HIGH
3.5V
1.5V
1.5V
0V
DISABLE
tPLZ
3V
1.5V
0V
3.5V
t PHZ
0.3V V OL
0.3V V OH
0V
NOTES
2605 drw 10
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0 MHz; ZO ≤ 50Ω; tF ≤ 2.5ns;
tR ≤ 2.5ns.
7.4 5
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet IDT54FCT139.PDF ] | |
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