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PDF IDT49FCT805CT Data sheet ( Hoja de datos )
| Número de pieza | IDT49FCT805CT | |
| Descripción | FAST CMOS BUFFER/CLOCK DRIVER | |
| Fabricantes | Integrated Device | |
| Logotipo |  |
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Integrated Device Technology, Inc.
FAST CMOS
BUFFER/CLOCK DRIVER
IDT49FCT805BT/CT
IDT49FCT806BT/CT
FEATURES:
• 0.5 MICRON CMOS Technology
• Guaranteed low skew < 500ps (max.)
• Very low duty cycle distortion < 600ps (max.)
• Low CMOS power levels
• TTL compatible inputs and outputs
• TTL level output voltage swings
• High drive: -32mA IOH, 48mA IOL
• Two independent output banks with 3-state control
• 1:5 fanout per bank
• ‘Heartbeat’ monitor output
• ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
• Available in DIP, SOIC, SSOP, QSOP, Cerpack and
LCC packages
FUNCTIONAL BLOCK DIAGRAMS
• Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The IDT49FCT805BT/CT and IDT49FCT806BT/CT are
clock drivers built using advanced dual metal CMOS technol-
ogy. The IDT49FCT805BT/CT is a non-inverting clock driver
and the IDT49FCT806BT/CT is an inverting clock driver. Each
device consists of two banks of drivers. Each bank drives five
output buffers from a standard TTL compatible input. The
805BT/CT and 806BT/CT have extremely low output skew,
pulse skew, and package skew. The devices has a "heart-
beat" monitor for diagnostics and PLL driving. The MON
output is identical to all other outputs and complies with the
output specifications in this document. The 805BT/CT and
806BT/CT offer low capacitance inputs with hysteresis.
IDT49FCT805T
IDT49FCT806T
OEA
INA
INB
5
OA1-OA5
5
OB1-OB5
OEA
INA
INB
5 OA1-OA5
5 OB1-OB5
OEB
MON
2920 drw 01
OEB
MON
2920 drw 02
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996 Integrated Device Technology, Inc.
9.2
OCTOBER 1995
DSC-2920/5
1
1 page  
IDT49FCT805BT/CT, 806BT/CT
FAST CMOS BUFFER/CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE(3,4)
IDT49FCT805BT/806BT IDT49FCT805CT/806CT
Com'l. Mil. Com'l. Mil.
Symbol
Parameter
tPLH Propagation Delay
tPHL INA to OAn, INB to OBn
tR Output Rise Time
Condition(1)
CL = 50pF
RL = 500Ω
Min.(2)
1.5
—
Max.
5.0
1.5
Min.(2)
1.5
—
Max.
5.7
2.0
Min.(2)
1.5
—
Max.
4.5
1.5
Min.(2)
1.5
—
Max.
5.2
2.0
Unit
ns
ns
tF Output Fall Time
— 1.5 — 1.5 — 1.5 — 1.5 ns
tSK(o) Output skew: skew between outputs of all
banks of same package (inputs tied together)
— 0.7 — 0.9 — 0.5 — 0.7 ns
tSK(p) Pulse skew: skew between opposite
transitions of same output (|tPHL–t PLH|)
— 0.7 — 0.9 — 0.6 — 0.8 ns
tSK(t)
Package skew: skew between outputs of
different packages at same power supply
voltage, temperature, package type and
speed grade
— 1.2 — 1.5 — 1.0 — 1.2 ns
tPZL Output Enable Time
tPZH OEA to OAn, OEB to OBn
1.5 6.0 1.5 6.5 1.5 5.0 1.5 6.0 ns
tPLZ Output Disable Time
tPHZ OEA to OAn, OEB to OBn
1.5 6.0 1.5 6.5 1.5 5.0 1.5 6.0 ns
NOTES:
2920 tbl 07
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. tPLH, tPHL, tSK(t) are production tested. All other parameters guaranteed but not production tested.
4. Propagation delay range indicated by Min. and Max. limit is due to VCC, operating temperature and process parameters. These propagation delay
limits do not imply skew.
9.2 5
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| PDF Descargar | [ Datasheet IDT49FCT805CT.PDF ] | |
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