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PDF IDT49FCT20805PYI Data sheet ( Hoja de datos )
| Número de pieza | IDT49FCT20805PYI | |
| Descripción | 2.5V CMOS DUAL 1-TO-5 CLOCK DRIVER | |
| Fabricantes | Integrated Device | |
| Logotipo |  |
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IDT49FCT20805
2.5V CMOS DUAL 1-TO-5 CLOCK DRIVER
2.5V CMOS DUAL
1-TO-5 CLOCK DRIVER
INDUSTRIALTEMPERATURERANGE
IDT49FCT20805
FEATURES:
• Advanced CMOS Technology
• Guaranteed low skew < 200ps (max.)
• Very low propagation delay < 2.5ns (max)
• Very low duty cycle distortion < 270ps (max)
• Very low CMOS power levels
• Operating frequency up to 166MHz
• TTL compatible inputs and outputs
• Two independent output banks with 3-state control
• 1:5 fanout per bank
• "Heartbeat" monitor output
• VCC = 2.5V ± 0.2V
• Available in SSOP and QSOP packages
DESCRIPTION:
The FCT20805 is a 2.5 volt clock driver built using advanced CMOS
technology. Thedeviceconsistsoftwobanksofdrivers,eachwitha1:5fanout
and its own output enable control. The device has a "heartbeat" monitor for
diagnostics and PLL driving. The MON output is identical to all other outputs
and complies with the output specifications in this document. The FCT20805
offers low capacitance inputs.
The FCT20805 is designed for high speed clock distribution where signal
quality and skew are critical. The FCT20805 also allows single point-to-point
transmission line driving in applications such as address distribution, where one
signal must be distributed to multiple recievers with low skew and high signal
quality.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
OEA
INA
INB
OEB
5
OA1 - OA5
5
OB1 - OB5
MON
VCCA
OA1
OA2
OA3
GNDA
OA4
OA5
GNDQ
OEA
INA
1
2
3
4
5
6
7
8
9
10
20 VCCB
19 OB1
18 OB2
17 OB3
16 GNDB
15 OB4
14 OB5
13 MON
12 OEB
11 INB
SSOP/ QSOP
TOP VIEW
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
c 2003 Integrated Device Technology, Inc.
1
FEBRUARY 2003
DSC-6172/8
1 page  
IDT49FCT20805
2.5V CMOS DUAL 1-TO-5 CLOCK DRIVER
TEST CIRCUITS AND WAVEFORMS
VCC
Pulse
Generator
VIN
D.U.T
RT
VOUT
RL
INDUSTRIALTEMPERATURERANGE
4.6V
Open
GND
500Ω
CL 500Ω
Enable and Disable Time Circuit
VCC
Pulse
Generator
VIN
D.U.T
RT
VOUT
RL
CL
CL = 15pF Test Circuit
INPUT
OUTPUT 1
OUTPUT 2
tPLH1
tPHL1
tSK(o)
tSK(o)
tPLH2
tPHL2
2.5V
1.25V
0V
VOH
1.25V
VOL
VOH
1.25V
VOL
tSK(o) = |tPLH2 - tPLH1| or |tPHL2 - tPHL1|
Output Skew - tSK(O)
SWITCH POSITION
Test
Disable Low
Enable Low
Disable High
Enable High
Switch
4.6V
GND
TEST CONDITIONS
Symbol
CL
RT
RL
tR / tF
VCC = 2.5V ±0.2V
15
ZOUT of pulse generator
33
1 (0V to 2.5V or 2.5V to 0V)
Unit
pF
Ω
Ω
ns
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
tR / tF = Rise/Fall time of the input stimulus from the Pulse Generator.
5
5 Page | ||
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| PDF Descargar | [ Datasheet IDT49FCT20805PYI.PDF ] | |
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