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PDF M66252FP Data sheet ( Hoja de datos )
| Número de pieza | M66252FP | |
| Descripción | 1152 x 8-BIT LINE MEMORY FIFO | |
| Fabricantes | Mitsubishi | |
| Logotipo |  |
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MITMSITUSBUISBHISI H〈DI I〈GDIITGAITLAALSASSPS〉 P〉
M662M5626P25/2FPP/FP
1151215x28x-B8IT-BLITINLEINMEEMMEOMROYR(FYIF(FOIF) O)
DESCRIPTION
The M66252P/FP is a high-speed line memory with a FIFO
(First In First Out) structure of 1152-word × 8-bit configuration
which uses high-performance silicon gate CMOS process
technology.
It has separate clock, enable and reset signals for write and
read and is most suitable as a buffer memory between
devices with different data processing throughput.
FEATURES
• Memory construction ........................................................
............................. 1152words x 8bits (dynamic memory)
• High-speed cycle ............................................ 50ns (min.)
• High-speed access ........................................ 40ns (max.)
• Output hold ....................................................... 5ns (min.)
• Fully independent, asynchronous write and read opera-
tions
• Variable-length delay bit
• Output .................................................................... 3-state
APPLICATION
Digital photocopiers, high-speed facsimiles, laser beam print-
ers.
PIN CONFIGURATION (TOP VIEW)
Q0
Data output Q1
Q2
Q3
Read enable input RE
Read reset input RRES
GND
Read clock input RCK
Q4
Q5
Data output
Q6
Q7
1
2
3
4
5
6
7
8
9
10
11
12
24 D0
23 D1
22 D2
Data input
21 D3
20 WE Write enable input
19 WRES Write reset input
18 VCC
17 WCK Write clock input
16 D4
15 D5
14 D6
Data input
13 D7
Outline
24P4Y
24P2W-A
BLOCK DIAGRAM
Write
enable input
WE 20
Write
reset input
WRES
19
Write
clock input
WCK 17
Vcc 18
Data input
D0 D1 D2 D3 D4 D5 D6 D7
24 23 22 21 16 15 14 13
Data output
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
1 2 3 4 9 10 11 12
Input buffer
Output buffer
Memory array
(1152 x 8 bits)
5
RE
Read
enable input
6
RRES
Read
reset
input
8
RCK
Read
clock input
7 GND
1
1 page  
MITSUBISHI 〈DIGITAL ASSP〉
M66252P/FP
TIMING CHARTS
• Write Cycles
Cycle n Cycle(n+1) Cycle(n+2)
WCK
tWCK
tWCKH tWCKL tWEH tNSES
1152 x 8-BIT LINE MEMORY (FIFO)
Disable cycles
Cycle(n+3) Cycle(n+4)
tNWEH tWES
WE
tDS tDH
tDS tDH
Dn
(n)
(n+1)
(n+2)
(n+3)
(n+4)
WRES=“H”
• Write Reset Cycles
WCK
Cycle(n–1) Cycle n
tWCK tNRESH tRESS
Reset cycles
Cycle 0
Cycle 1
Cycle 2
tRESH tNRESS
WRES
Dn
tDS tDH
tDS tDH
(n –1)
(n)
(0) (1) (2)
WE=“L”
5
5 Page 
MITSUBISHI 〈DIGITAL ASSP〉
M66252P/FP
1152 x 8-BIT LINE MEMORY (FIFO)
APPLICATION EXAMPLE
Laplacian Filter Circuit for Correction of Resolution in the Secondary Scanning Direction.
B
Line (n+1)
image data
M66252
D0 Q0
D7 Q7
1-line
delay
N
Line n image data
×2
M66252
D0 Q0
D7 Q7
A
Line (n–1)
image data
1-line
delay
×K
Corrected
image data
Primary scanning
direction
A
N
B
Line (n–1)
Line n
Line (n+1)
N' = N+K {(N–A)+(N–B)}
= N+K {2N–(A+B)}
K : Laplacean coefficient
11
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet M66252FP.PDF ] | |
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