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PDF M65762FP Data sheet ( Hoja de datos )
| Número de pieza | M65762FP | |
| Descripción | QM-CODER(purpose of reducing) | |
| Fabricantes | Mitsubishi | |
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MITSUBISHI SEMICONDUCTOR (LSI)
M65762FP
QM-CODER
DESCRIPTION
The M65762FP is a compression and decompression LSI
conforming to the high efficiency encoding system (QM-Coder) in
the International Standard, the JBIG/JPEG (ITU-T Recommenda-
tions T.81 and T.82) for coding still images. It also conforms to the
International Standard (ITU-T Recommendation T.85) for facsimile.
The QM-Coder is an information dependent type which is capable
of completely restoring original image data, and is equipped with
the learning function to always optimize parameters according to
the statistical characteristics of images. The QM-Coder is therefore
superior in compression ratio compared with the existing binary
coding system (MH/MR/MMR) and can greatly improve the half
toning image (dithered half toning image) whose compression ratio
is especially poor.
FEATURES
• Completely conforms to the International Standard (ITU-T T.85)
for facsimile.
• Achieves encoding/decoding with the arithmetic coder (QM-
Coder) conforming to the recommendation of the International
Standard JBIG/JPEG.
• Is expected to conform to the International Standard for color
facsimile (T.Pallete-colour).
• High speed processing that puts into effect coding and decoding
at 40 million pixels per sec maximum.
• Is possible data-through processing without coding and decodin.
• Can select context
• Provides 10 pixel template model for minimum resolution
conforming to JBIG and can select 2-line or 3-line template
model.
• Built-in typical prediction function
• Capable of coding and decoding by using the typical prediction.
• Since use of the typical prediction does not require the
processing of the line (TP line) which is matched the previous
line's data, is capable of reducing data and processing time.
• Built-in adaptive template (AT) function
• Is capable of setting AT pixels before 127 pixels on the coding
line.
• Since It is possible to change the position of AT pixel in a
specified line, is capable of improving compression
characteristics even when image characteristic is changed in
the middle of the screen.
• Supporting multi-stripe
• When a page consists of more than one stripe, is capable of
repeating encoding/decoding process in stripes.
• Built-in load/store function of line memory Supporting multiple
planes and multi-stripe function
• Is capable of loading image data for reference line from
outside to line memory of the LSI and storing image data from
line memory to outside.
• Number of processing lines
• Is capable of issuing the start of processing (temporary stop
command) several times to encode/decode any lines more
than or equal to 65535 lines.
• Supporting 3-bus interface
• An 8-bit host bus corresponds to the MPU is available to load
and store of context table RAM.
• For input/output of binary image data, is capable of performing
32-bit or 16-bit parallel or serial input/output.
• For input/output of coding data, is capable of selecting 32-
bit/16-bit/8-bit bus to perform DMA transfer of coding data.
• Is capable of making scale-down for coding and scale-up for
decoding.
• Is capable of setting marker code for coding and detecting
marker code for decoding.
• Built-in RAM for 4096 bytes for line memory, built-in context table
RAM and built-in probability estimation table ROM of 113 status
• +5V single power supply
APPLICATION
• OA equipment including facsimile, copier and printer
• Digital and amusement equipment for the purpose of reducing
memory
1 page  
MITSUBISHI SEMICONDUCTOR (LSI)
M65762FP
QM-CODER
Description on Pin Functions
I/F Pin name
I/O BUF
(Asterisk "*" in signal name indicates negative logic.)
Function
RESET*
HCS*
HA0-3
HWR*
HRD*
HD0-7
INTR
I S H/W reset signal
I Chip select signal
I Address select signal of internal register
I S Write strobe signal
I S Read strobe signal
I R8 Input/output data bus signal
O 4 Interrupt request signal
CD0-31
CDRQ
CDAK*
CDRD*
CDWR
I/O UR8
O4
I US
I US
I US
Coding data input/output bus signal
(CD0-15 is used in 16-bit bus and CD0-7 is used in 8-bit bus.)
DMA request signal for coding data (image data)
DMA acknowledge signal for coding data (image data)
Read strobe signal for coding data (image data)
Write strobe signal for coding data (image data)
PD0-31
PDRQ
PDAK*
PDRD*
PDWR*
I/O UR8
O4
I US
I US
I US
Parallel image data input/output bus (PD0-15 is used in 16-bit bus.)
DMA request signal for image data
DMA acknowledge signal for image data
Read strobe signal for image data
Strobe signal for image data
PRDY*
PTIM*
PXCK*
PXCKO*
SVID*
RVID*
O4
I US
I US
O4
IU
O4
1-line input/output start ready signal for image data
1-line transfer sector signal for image data
Transfer clock signal for image data
Transfer clock signal for image data (LSI internal loopback output signal of PXCK*)
Image data input signal
Image data output signal
MCLK
TEST0, 1
I
I DS
Master clock input signal
Test input signal 0/1 (Should be connected to GND when used normally.)
VDD
GND
––
––
Power supply (+5V)
Ground
• Input buffer for the input pins ("I" and "IO") are set at the TTL level and the options are as follows.
(U: Having pull-up resistance, D: Having pull-down resistance, S: Schmitt trigger, R: Through rate control)
• Numbers (4, 8) in the BUF column for the output pins ('O' and 'IO') indicate Io (= 4 or 8 mA).
Specifications
(1) Package
Plastic QFP 144 pins (20 mm*20 mm)
(2) Power consumption
5V 120mA (600mW)
(3) Maximum clock frequency
40MHz
5 Page 
MITSUBISHI SEMICONDUCTOR (LSI)
M65762FP
QM-CODER
(6) Register for setting the number of pixels (W/R)
d7
(Address: 4) PEL_REG_L:
(Address: 5) PEL_REG_H: 0
d7
PEL_L
PEL_H
d5
d0
d0
d0-7 (PEL_L) :Sets the number of pixels in a line. (Low byte)
d0-5 (PEL_H) :Sets the number of pixels in a line. (Upper byte)
A maximum of 8192 pixels can be set at the 3-line
template. A maximum of 10240 pixels can be set
at the 2-line template.
Set the number of pixels to be actually coded
(decoded) at time of scale-up (scale-down).
When the image data bus is 16-bits (32-bits) with
the parallel I/F selected, set the number of pixels to
multiples of 16 (multiples of 32).
With the serial I/F selected, set the number of
pixels to multiples of 8.
(7) Register for setting the number of lines (W/R)
d7
(Address: 6) LSET_REG_L:
LSET_L
(Address: 7) LSET_REG_H:
LSET_H
d0
d0-7 (LSET_L) :Sets the number of lines to be processed. (Low
order byte) (1 to 65535: 0 line is not allowed.)
d0-7 (LSET_H) :Sets the number of lines to be processed. (High
order byte)
At time of scale-down (scale-up), set the number of
lines to be actually coded (decoded).
Set the number of lines (number of relative lines)
ranging from the processing start command to be
issued next to the temporary stop/termination end
just after. This register must be set to a specific
value before the issuance of the process start
command.
As far as the following conditions are satisfied, this
register can be rewritten in the course of
processing.
•When the maximum value (65535) is set before
issuance of the processing start command, an
arbitrary value can be set once in the course of
processing.
•When a value except for the maximum value
(65535) is set before issuance of the processing
start command, and the value requires to be
respecified in the course, respecify the maximum
value (65535) once and then respecify a desired
value.
87 6
543 29
10?
3-line template
8543 2 9
7610 ?
2-line template
Figure 4. Address Assignment of Context Table RAM
(Number for address bit (LSB: 0, MSB: 9), MSB: 9 for AT pixel)
(8) Processing line count register (R)
d7
(Address: 8) LIN_REG_L:
(Address: 9) LIN_REG_H:
LINE_L
LINE_H
d0
d0-7 (LINE_L) :Read out the number of lines actually processed
(low byte) (0 to 65535)
d0-7 (LINE_H) :Read out the number of lines actually processed
(upper byte)
The number of processed lines ≥ number of set
lines, coding/decoding/through processing stop
temporary/end of processing.
(Note)The number of lines in this process is cleared
to 0 with the processing start command issued.
(9) Buffer register (W/R)
(Address: A) DWR_BUF:
d7
DWR
d0
d0-7 (DWR)
:Data for loading/storing context table RAM
This register is a buffer for loading data into t h e
context table RAM via the host bus or for storing
data outside. After issuance of load/store start
command of the context table RAM (command
register d3 = 1), this register is available to start
loading or storing data. Prediction value (MPS) and
prediction unmatched probability (LSZ) can be
stored in context table RAM for a unit of 1024
contexts in total. Figure 4 and Table 4 provide the
address assignment of context table RAM and the
data bit array.
Since context table RAM is 2-byte data, access is
gained alternately in order from low byte to upper
byte. Each time two-byte access is gained, the
RAM address is automatically incremented
(sequential access from address 0).
(Note1)Data is not allowed to be loaded and stored
at a time. Random access to RAM is not
allowed.
(Note2)Only 133 types specified by the JBIG
international standard (See attached Figure
A.2) are allowed to be specified for the LSZ
value.
(For example, load '5a1d' for initialization.)
Table 4. Data Bit Array of Context Table RAM
High order byte
Low order byte
d15 d14 • • • • • d8
d7 • • • • • d0
MPS L14 • • • • • L8
L7 • • • • • L0
MPS :Prediction value MPS (0/1)
L14-0 :Low 15-bits of prediction unmatched probability LSZ
('0001' to '5b12')
11 Page | ||
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