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PDF M65675FP Data sheet ( Hoja de datos )
| Número de pieza | M65675FP | |
| Descripción | DIGITAL NTSC/PAL ENCODER | |
| Fabricantes | Mitsubishi | |
| Logotipo |  |
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PRELIMINARY
Notice:This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI ICs (TV)
M65675FP/M65676FP
DIGITAL NTSC/PAL ENCODER
DESCRIPTION
The M65675FP/M65676FP is a NTSC/PAL encoder LSI that
converts CCIR 601 or CCIR 656 (SMPTE125M) format digital video
signals into analog component and composite video signals in
accordance with either NTSC or B/G-PAL standards.
The 10-bit digital luma (Y) and analog chroma (U/V) signals are
available in Y/U/V output mode.
In addition it performs the closed caption capability (TV line 21/
NTSC), CGMS*1 encoding (TV line 20/NTSC), WSS*2 encoding (TV
line 23/PAL), Macrovision copy protection*3 function (Rev. 7.01) and
on-screen display. The OSD function can be directly accessed by
the OSD microprocessor via built-in interface.
FEATURES
• NTSC and B/G-PAL Outputs
• Component Y/C (S-Video), Composite (CVBS) or Y*4/U/V
Outputs
• Supporting CCIR601, CCIR656 (SMPTE125M) Format Data
• Processing Y/Cb/Cr and Y/U/V Pixel Data
• 27MHz Clock Frequency (Two-times Oversampling)
• Macrovision Copy Protection*3 Processing (Revision 7.01)
• Close Captioning Supporting (line 21/NTSC) (ODD Parity Opera-
tion)
• V-Code Supporting (line 21/NTSC) (ODD Parity Operation)
• CGMS*1 Data Insertion (line 20/NTSC) (CRCC Error Correction
Code Operation)
• WSS*2 Supporting (line23/PAL)
• OSD Insertion Interface and 3¥8¥4-bit Color Look-up Table
PIN CONFIGURATION (TOP VIEW)
• Controllable Picture Processing Functions
Color, TINT and Brightness
• Built-in Analog Functions
Y/C Mixing
Two 10-bit DACs
Three 6-dB Amplifiers
• Built-in 27 MHz System Clock Generator
• Single 3.3V Supply
• 64-pin PQFP Package
Note
*1: Copy Generation Management System-A (IEC1880)
*2: Wide Screen Signaling (ETS300 294)
*3: This applies to M65675FP only.
This device is protected by U.S. patent number 4631603,
4577216 and 4819098 and other intellectual property rights.
The use of Macrovision's copy protection technology in the
device must be authorized by Macrovision and is intend for
home and other limited pay-par-view use only, unless otherwise
authorized in writing by Macrovision. Reverse engineering or
disassembly is prohibited.
*4: Y output is 10bit digital signal.
APPLICATION
DVD Players, Digital Satellite & Cable System (Set Top Boxes/
IRDs), Video CD, Multimedia Terminals, Video Games, Digital VCR
& Camcoder etc.
Ycomp 49
N.C. 50
DVDD1 51
DVSS1 52
X out
53
X in 54
DVSS2 55
PXD7
56
PXD6
57
PXD5
58
PXD4
59
PXD3
60
PXD2
61
PXD1
62
PXD0
63
DVDD2 64
M65675FP
M65676FP
32 N.C.
31 N.C.
30 DVDD1
29 TEST
28 SCL
27 SDA
26 ACK
25 RESET
24 Master/slave
23 OSD2
22 OSD1
21 OSD0
20 OSDCK
19 DVSS1
18 DVDD1
17 DVDD2
Outline 64P6N-A
NC : NO CONNECTION
1
1 page  
PRELIMINARY
Notice:This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI ICs (TV)
M65675FP/M65676FP
DIGITAL NTSC/PAL ENCODER
◊ CCIR656 Interface
PXCLK=27.0MHz
Cb/Y/Cr=8-bit/27.0Mbps
Y=8-bit/27.0Mbps
16-235 straight-binary-data
Cb/Cr=8-bit/13.5Mbps (Cb=Cr=8-bit/6.75 Mbps)
16-240 128 offset-binary-data
Active video area 525/60=720-pixel¥480 line/frame
(22/284 line-263/525 line)
625/50=720-pixel¥576 line/frame
(23/336 line-310/623 line)
Vertical blanking Interval 525/60=1/264-9/272
Digital field 1 (ODD)=4-265
Digital field 2 (EVEN)=266-3
625/50=624/311-22/335
Digital field 1 (ODD)=1-312
Digital field 2 (EVEN)=313-625
Horizontal blanking Interval525/60=276CLK (0H=32CLK)
EAV=1-4CLK/SAV=273-276CLK
625/50=288CLK (0H=24CLK)
EAV=1-4CLK/SAV=285-288CLK
The input data (X), except the active data in the above support
format, are clipped as shown below;
◊ 8/16-bit CCIR601 Interface
Y : X£16 Æ 16
X≥235Æ235 (Whole period)
Cb/Cr : X£16 Æ 16
(U/V) X≥240Æ240 (Whole period)
◊ CCIR656 Interface
Y : X£16 Æ 16
X≥235Æ235
X Æ 16
Cb/Cr : X£16 Æ 16
(U/V) X≥240Æ240
X Æ 128
(Active video period)
(Blanking period)
(Active video period)
(Blanking period)
Digital Multiplexing
The input pixel data described in 4.1.1.1 are de-multiplexed, then Y,
Cb,Cr and Y, U, V signals will be converted to each 8-bit parallel
data. After the above conversion, 6.75Mbps Cb, Cr/U, V data are
interpolated at a double clock rate of 13.5Mbps.
PXCLK Processing
PXCLK is generated from the 27.0MHz system clock according to
the appropriate selected format and the clock signal for Y, Cb, Cr/Y,
U, V data de-multiplexing is also generated.
OSD Interface
Color Look-up Table (CLT)
The built-in CLT can be equivalent to 4bit¥8 colors, so that the
reproduced colors are 8/4096.
The setting ranges and the signal levels in the overlaying of Y, Cb
and Cr each are shown below;
Y : Setting range=1 (h) to F (h) : straight-binary data
Signal Level=10 (h) to F0 (h) : straight-binary data
Cb/Cr : Setting range=1 (h) to F (h) : 8 offset-binary data
Signal level=10 (h) to F0 (h) : 128 offset-binary data
OSD Control
Overlaying the appointed data on the video signal from MPEG is
possible by inputting the address data to the CLT in synchronization
with OSDCLK, H-sync and V-sync. The overlaying is prohibited in
case CLT address is set to 7 (h).
The OSD control specifications are shown below;
◊ OSDCLK= selectable 13.5MHz or 6.75MHz
selectable continuous or discontinuous
(pausing during H-sync) clock
◊ Color Signal Blend=Maximum 3 colors are allowed to be set.
The data of CLT addresses 0 (h) to 2 (h) are
dedicated to color blending.
The blend ratio is fixed by 1:1 and blend
mode is selectable between Y/Cmix and Ymix
mode.
Y/Cb/Cr to Y/U/V Converter
C-sync Addition
The sync signal, set up in the register, is added to Y signal
according to C-sync timing generated from H-sync/V-sync. Typical
sync height, set up in the register, is calculated by the following
equations;
Sync level={(White peak input level-16)¥2.5¥Xsync (IRE)}/100
In the case of NTSC : {(235-16)¥2.5¥40}/100=219 (DBH)
PAL : {(235-16)¥2.5¥43}/100=235.4 (EBH)
Note: Xsync=Output sync level (IRE)
Set-up Control (NTSC)
In the NTSC signal generation mode, three set-up modes are
possible according to the register.
Selectable set-up modes are;
Mode 0 : Set-upÆ0 IRE
Mode 1 : Set-upÆ+7.5 IRE
Mode 2 : Set-upÆ-7.5 IRE
Cb/Cr to U/V Conversion
The Cb/Cr data are converted into the U/V data by the following
equations;
U=0.493¥Cb/0.564
V=0.877¥Cr/0.713
5
5 Page 
PRELIMINARY
Notice:This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI ICs (TV)
M65675FP/M65676FP
DIGITAL NTSC/PAL ENCODER
Serial Register
The serial address register can be addressed by I2C bus.
The M65675FP/M65676FP has two slave addresses, 40 and 42h.
In the actual use, one of two is selected and then Pin 3 (DVASEL)
is set according to the selected address data
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Slave address=40h
0 1 0 0 0 0 0 R/W
42h 0 1 0 0 0 0 1 R/W
Register Mapping and Description
sub
address
Function
00 Write control
01
Interface
02
03 Sync level
04 Burst level
05 Sync delay
06 Y delay
07 TINT
08
Closed Caption (1st field)
09
0A
Closed Caption (2nd field)
0B
0C
CGMS/WSS
0D
0E OSD control
0F
10
11
12
13
14
Color Lookup Table
15
16
17
18
19
1A
1B
1C
1D
∗1
1E Macrovision
1F
20
Mode selection
Color Stripe
Definition #1
Color Stripe
Definition #2
Color Stripe
Definition #3
Color Stripe
Definition #4
Color Stripe
Definition #5/6/7
data
76543210
WE
P-save UVin
YCINV
CbCrINV
Color
Bar
525/
625
NTSC/
PAL
YC/UV
SCH
offset
Setup1
Setup0
CGMS
/WSS
CC1F CC2F CCI/F CCD1 CCD0 CCIR1 CCIR0
sync7 sync6 sync5 sync4 sync3 sync2 sync1 sync0
burst6 burst5 burst4 burst3 burst2 burst1 burst0
SD4 SD3 SD2 SD1 SD0
YD4 YD3 YD2 YD1 YD0
TINT7 TINT6 TINT5 TINT4 TINT3 TINT2 TINT1 TINT0
CC106 CC105 CC104 CC103 CC102 CC101 CC100
CC116 CC115 CC114 CC113 CC112 CC111 CC110
CC206 CC205 CC204 CC203 CC202 CC201 CC200
CC216 CC215 CC214 CC213 CC212 CC211 CC210
CG08/ CG07/ CG06/ CG05/ CG04/ CG03/ CG02/ CG01/
WS07 WS06 WS05 WS04 WS03 WS02 WS01 WS00
CG14/ CG13/ CG12/ CG11/ CG10/ CG09/
WS13 WS12 WS11 WS10 WS09 WS08
CLTEN
OSD
CLK
BLD
mode
BLD1
BLD0
CTY13 CTY12 CTY11 CTY10 CTY03 CTY02 CTY01 CTY00
CTB13 CTB12 CTB11 CTB10 CTB03 CTB02 CTB01 CTB00
CTR13 CTR12 CTR11 CTR10 CTR03 CTR02 CTR01 CTR00
CTY33 CTY32 CTY31 CTY30 CTY23 CTY22 CTY21 CTY20
CTB33 CTB32 CTB31 CTB30 CTB23 CTB22 CTB21 CTB20
CTR33 CTR32 CTR31 CTR30 CTR23 CTR22 CTR21 CTR20
CTY53 CTY52 CTY51 CTY50 CTY43 CTY42 CTY41 CTY40
CTB53 CTB52 CTB51 CTB50 CTB43 CTB42 CTB41 CTB40
CTR53 CTR52 CTR51 CTR50 CTR43 CTR42 CTR41 CTR40
CTY63 CTY62 CTY61 CTY60
CTB63 CTB62 CTB61 CTB60
CTR63 CTR62 CTR61 CTR60
N16 [0] N0 [6] N0 [5] N0 [4] N0 [3] N0 [2] N0 [1] N0 [0]
N21 [1] N21 [0] N1 [5] N1 [4] N1 [3] N1 [2] N1 [1] N1 [0]
N2 [5] N2 [4] N2 [3] N2 [2] N2 [1] N2 [0]
N3 [5] N3 [4] N3 [3] N3 [2] N3 [1] N3 [0]
N4 [6] N4 [5] N4 [4] N4 [3] N4 [2] N4 [1] N4 [0]
N7 [1] N7 [0] N6 [2] N6 [1] N6 [0] N5 [2] N5 [1] N5 [0]
11
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet M65675FP.PDF ] | |
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