|
|
PDF M65617SP Data sheet ( Hoja de datos )
| Número de pieza | M65617SP | |
| Descripción | PICTURE-IN-PICTURE SIGNAL PROCESSING | |
| Fabricantes | Mitsubishi | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de M65617SP (archivo pdf) en la parte inferior de esta página. Total 15 Páginas | ||
|
No Preview Available !
MITSUBISHI ICs (TV)
M65617SP
PICTURE-IN-PICTURE SIGNAL PROCESSING
DESCRIPTION
This system is an NTSC system PinP system that accommodates
subscreen composite input and main screen Y/C input. It is a
semiconductor IC circuit having a built-in 96K bit field memory and
an analog circuit, which permits a low-cost and compact system
configuration.
FEATURES
• Built-in field memory 96K bit for PIP
• Built-in luminance signal vertical filter
• No. of subscreen displays: 1 (two sizes, 1/9 and 1/16, can be
selected from.)
• No. of subscreen samples (1/9 - 1/16 sizes)
No. of quantization bits: 6 for all Y, B-Y and R-Y
No. of horizontal picture elements: 171(Y), 28.5 (B-Y, R-Y)
No. of vertical lines: 69/52
• Subscreen frame display ON/OFF
• Built-in analog circuits such as sync chip clamp, VCXO, and ana-
log switch
• Built-in 2 channels of 8 bit A/D converter
(for main signal burst lock and PIP sub signal)
• Built-in two channels of 8 bit D/A converter (luminance and
chroma signals)
• I2C bus control
Controls: display ON/OFF, display size selection, setting of
display position, frame ON/OFF, setting of frame level, selection
of frame animation/field still image, setting of Y delay amount,
color level, tint, black level, etc.
APPLICATION
TV
RECOMMENDED OPERATING CONDITION
Supply voltage range........................................................3.1 to 3.5V
Operating frequency.........................................................14.32 MHz
Operating temperature....................................................-10 to 75°C
Input voltage (CMOS interface) "H"........................VDD×0.7 to VDD V
"L".............................0 to VDD×0.3V
Output current (output buffer)........................................±4mA (MAX)
Output load capacitance............................................20pF (MAX) ∗1
Circuit current.........................................................................140mA
NOTICE: Connect a 0.1µF or larger capacitor between VDD and VSS
pins.
∗1 : Include pin capacitance (7pF)
PIN CONFIGURATION (TOP VIEW)
AVss3 (vcxo) 1
VCXO out 2
VCXO in 3
FILTER 4
BIAS 5
AVdd3 (vcxo) 6
AVdd2 (m) 7
Vin (m) 8
Vrt (m) 9
Vrb (m) 10
AVss2 (m) 11
AVdd1 (s) 12
Vin (s) 13
Vrt (s) 14
Vrb (s) 15
AVss1 (s) 16
RESET 17
DVss1 18
DVdd1 19
BGP(s)/TEST0 20
SCK 21
CSYNC(s)/TEST1 22
ACK 23
DATA 24
CLK 25
DVss2 26
52 AVssf (ana)
51 Cin
50 TESTEN
49 Yin
48 TEST9
47 Y-PIP
46 TEST8
45 C-PIP
44 AVdd4 (da)
43 C-PIPin
42 AVss4 (da)
41 Y-PIPin
40 ADJ-Ysub
39 Yout-sub
38 ADJ-Csub
37 Cout-sub
36 DVss3 (ram)
35 DVdd3 (ram)
34 SWMG/TEST7
33 VD/CSYNC/TEST6
32 HD/TEST5
31 SWM/TEST4
30 MCK
29 fsc/TEST3
28 BGP(m)/TEST2
27 DVdd2
Outline 52P4B
1
1 page  
MITSUBISHI ICs (TV)
M65617SP
PICTURE-IN-PICTURE SIGNAL PROCESSING
SERIAL REGISTER INFORMATION (device address=24h, sub-address=00h to 0Fh)
Registers requiring user selection/adjustment setting are enclosed in rectangles.
Indication method of reference setting column: Thick letters: Fixed setting value
Standard letters: An example as setting for evaluation
∗/∗: 1/9 - 1/16 sizes
Sub-
address
00h
01h
02h
03h
04h
Bit No.
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
Reference
setting
Register name
1 color (0)
1 color (1)
1 color (2)
1 color (3)
1 color (4)
1 color (5)
1 color (6)
0 killer
0 tint (0)
0 tint (1)
0 tint (2)
0 tint (3)
0 tint (4)
0 tint (5)
0 afcoff
7 NB decode
0 0 evenupra
1 0 bgcs
2 0 extport (0)
3 1 extport (1)
4 0 adclocksel (0)
5 0 adclocksel (1)
6 1 mode (0)
7 0 mode (1)
0 1 crtint (0)
1 1 crtint (1)
2 1/0 size-h
3 0 hpfoff
NB bgpmsel
4 1 in case of 03h<7>(rvs)=1 or
03h<6>(rvhs)=1,
0 in other cases
5 0/1 size
6 0 rvhs
7 0 rvs
0 0 ydl (0)
1 0 ydl (1)
2 1 ydl (2)
3 0 ydl (3)
4 0 test acc lvl
5 1 wen
6 1 grc
7 NB stnby=testreset
Function
Color saturation adjustment; min. value [0], max. value[63], 1/step [3Fh setting]
[1 setting]
Color killer; ON [0], OFF [1], [0 setting]
Tint adjustment; setting by complements of 2
0fl to -50fl [00h to 1Fh]
+50fl to 0fl [20h to 3Fh]
[Normally 00h setting]
[0 setting]
Initialization of sub-screen color demodulation; normally [0], initialized [1]
Each time reset is cleared and sub-screen input source changed, operate in a
sequence of 0 - 1 - 0.
Setting of interlace leading line; leading field first/second [1/0], [0 setting]
Forced writing of background level [1 significant, normally 0] [0 setting]
I2C bus expansion port data (optional function); [Set to either of them]
Selection of adc clock delay; [00b setting]
Selection of IC operation mode; [01b setting] 16 bits [0]
Setting of sub-screen tint offset; [11b setting]
Horizontal size
Emphasis of high luminance signal area ON/OFF [0/1] [0 setting]
Selection of PIP-Y output clamping pulse; [0 setting when PIP is displayed]
Vertical size
Addition of sync, burst; OFF/ON [0/1] [Normally 0 setting when PIP is displayed]
Sync operation; Main input is followed [0], self-propelled [1] [0 setting when PIP is
displayed]
Setting of sub-screen Y delay amount
(D/A output phase against color signal); [4 setting]
Min. 280ns [0h], center 0ns [4h], max. +770ns [Fh]
acc reference level setting authorization; [1 significant] [0 setting]
Display of field still screen/display of animation [0/1]
Display of sub-screen frame; NO/YES [0/1]
[0] setting (memory access not operated by [1])
5
5 Page 
APPLICATION EXAMPLE
MITSUBISHI ICs (TV)
M65617SP
PICTURE-IN-PICTURE SIGNAL PROCESSING
Ana.
68p 470
Ana.
Ana.
10µ
104 104
Ana. 103
150p 360
Dig
10µ
15k 104 104 103 103 103
52 50 45 40 35
M65617SP
Dig
15k
30 27
103
10µ
15
10 15
20
26
Dig5V Digital +5V
power supply
Dig Digital +3.3V
power supply
Digital GND
Ana. Analog +3.3V
power supply
Analog GND
820k
12p X1 10p
100k
2.2µ
CX
2k
103
104 103 103
300
154
224
10µ
1.5µ
103
103
Ana.
Ana.
10µ
103
Ana.
Ana.5VAnalog +5V
power supply
Composite video
input signal
(sub-picture)
SYNC SEP
CIRCUIT
(OPTIONAL)
Y
103 103
10µ
103
104
100k
Dig5V
10µ
Dig
330 100
560 100
Dig5V
10k
100
C
10k
I2C BUS Clock
input signal
I2C BUS DATA
input/output
signal
Separate Y/C signals by using LC-tank circuit or LPF,BPF for Y/C signals level adjust.
And then mix both signals for sub-picture input video signal.
(The above external circuit processing aims at controlling white compression of
sub-screen input luminance signal and strengthening the color playback function of
sub-screen input signal in the case of weak electric field.)
Units Resistance : Ω
Capacitance : F
11
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet M65617SP.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| M65617SP | PICTURE-IN-PICTURE SIGNAL PROCESSING | Mitsubishi |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |