PDF M64894GP Data sheet ( Hoja de datos )

Número de pieza	M64894GP
Descripción	SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR
Fabricantes	Mitsubishi
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No Preview Available ! MITSUBISHI ICS (TV) M64894FP/GP SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR DESCRIPTION The M64894 is a semiconductor integrated circuit consisting of PLL frequency synthesizer for TV/VCR using I2C BUS control. It contains the prescaler with operating up to 1.3GHz, 4 band drivers and tuning Ampliﬁer for direct tuning. Built-in 4 band drivers. FEATURES • 4 integrated PNP band drivers (Io=40mA,Vsat=0.2V typ@Vcc1 to 13.2V) • Built-in high-withstanding voltage tuning Ampliﬁer • Low power dissipation (Icc=20mA, Vcc=5V) • Built-in prescaler with input ampliﬁer (Fmax=1.3GHz) • I2C bus control (Read and write mode) • X’tal 4MHz is used to realize 3 type of tuning steps (Division ratio 1/512, 1/640, 1/1024) • Built-in 5-level A/D converter • Programmable chip address • 16-pin small SOP/SSOP package APPLICATION TV, VCR tuners RECOMMENDED OPERATING CONDITION Supply voltage range..............................................VCC1=4.5 to 5.5V VCC2=VCC1 to 13.2V VCC3=28 to 35V Rated supply voltage...........................................................VCC1=5V VCC2=12V VCC3=33V PIN CONFIGURATION (TOP VIEW) PRESCALER INPUT GND SUPPLY VOLTAGE 1 SUPPLY VOLTAGE 2 BAND SWITCHING OUTPUTS fin 1 GND 2 VCC1 3 VCC2 4 BS4 5 BS3 6 BS2 7 BS1 8 16 Xin 15 ADS 14 SDA 13 SCL 12 ADC 11 VCC3 10 Vtu 9 Vin CRYSTAL OSCILLATOR CHIP ADDRESS INPUT DATA INPUT CLOCK INPUT A/D INPUT SUPPLY VOLTAGE 3 TUNING OUTPUT FILTER INPUT Outline 16P2S-A (FP) 16P2Z-A (GP) FUNCTION • 2-modulus prescaler (1/32 and 1/33) • Built-in 4MHz crystal oscillator and reference divider • Programmable divider (10-bit M counter, 5-bit S counter) • Tri-state phase comparator • Lock detector • Band switch driver • Op. Amp for direct tuning • I2C bus receiver • 5-level A/D converter 1 1 page MITSUBISHI ICS (TV) M64894FP/GP SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR METHOD OF SETTING DATA The input information to consit of 2 or data of 4bytes to lead to Chip Address is received in I2Cbus receiver. It shows a deﬁnition of bus protocol admitted in the following. 1_STA CA CB BB STO 2_STA CA D1 D2 STO 3_STA CA CB BB D1 D2 STO 4_STA CA D1 D2 CB BB STO STA : Start condition STO : Stop condition CA : Chip address CB : Control data byte BB : BandS.W. data byte D1 : Divider data byte D2 : Divider data byte The information of 5 bytes necessary for circuit operation is chip address and control data, bandS.W. data of 2 bytes and divider byte of 2 bytes. After the chip address input, 2 or data of 4 bytes are received. Function bit is contained the ﬁrst and the third data byte to distinguish between divider data and control data, band data, and "0" goes ahead of divider data, and "1" goes ahead of control data, bandS.W. data. SDA SCL S STA 1-7 ADDRESS CA 8 0 9 ACK 1-7 8 DATA 9 ACK 1-7 8 DATA 9 ACK P STO Write mode format Address Byte Devider Byte1 Devider Byte2 Control Byte1 Band SW Byte Byte MSB LSB 1 1 0 0 0 MA1 MA0 0 A 0 N14 N13 N12 N11 N10 N9 N8 A N7 N6 N5 N4 N3 N2 N1 N0 A 1 CP T2 T1 T0 RSa RSb OS A X X X X BS4 BS3 BS2 BS1 A Read mode format Address Byte Status Byte1 Byte MSB LSB 1 1 0 0 0 MA1 MA0 1 A POR FL X X X A2 A1 A0 A 5 5 Page

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