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PDF M64892GP Data sheet ( Hoja de datos )
| Número de pieza | M64892GP | |
| Descripción | SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR | |
| Fabricantes | Mitsubishi | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de M64892GP (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
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MITSUBISHI ICS (TV)
M64892AFP/GP
SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR
DESCRIPTION
The M64892 is a semiconductor integrated circuit consisting of
PLL frequency synthesizer for TV/VCR using Bip process. It
contains the prescaler with operating up to 1.0GHz, 4 band drivers
and Op. Amp for direct tuning.
FEATURES
• 4 integrated PNP band drivers
(Io=40mA,Vsat=0.2V typ@Vcc1 to 13.2V)
• Built-in Op. Amp for direct tuning voltage output (33V)
• Low power dissipation (Icc=20mA, Vcc1=5V)
• Built-in prescaler with input amplifier (Fmax=1.0GHz)
• PLL lock/unlock status display out put
(Built-in pull up resistor )
• X’tal 4MHz is used to realize 3 type of tuning steps
(Division ratio 1/512, 1/640, 1/1024)
• Serial data input. (3 wire bus)
• Software and pin compatible with M64092/M64892
• Automatic switching of tuning step according to the number of
data bits (62.5kHz at 18bits, 31.25kHz at 19bits)
• Built-in Power on reset system
• 16-pin small SOP/SSOP package
APPLICATION
TV, VCR tuners
RECOMMENDED OPERATING CONDITION
Supply voltage range..............................................VCC1=4.5 to 5.5V
VCC2=VCC1 to 13.2V
VCC3=28 to 35V
Rated supply voltage...........................................................VCC1=5V
VCC2=12V
VCC3=33V
PIN CONFIGURATION (TOP VIEW)
PRESCALER
INPUT
GND
SUPPLY
VOLTAGE 1
SUPPLY
VOLTAGE 2
BAND
SWITCHING
OUTPUTS
fin 1
GND 2
VCC1 3
VCC2 4
BS4 5
BS3 6
BS2 7
BS1 8
16 Xin
15 ENA
14 DATA
CRYSTAL
OSCILLATOR
ENABLE
INPUT
DATA INPUT
13 CLK CLOCK INPUT
12
LD/ftest
LD/ftest
OUTPUT
11 VCC3
SUPPLY
VOLTAGE 3
10 Vtu
TUNING
OUTPUT
9 Vin FILTER INPUT
Outline 16P2S-A (AFP)
16P2Z-A (AGP)
FUNCTION
• 2-modulus prescaler (1/32 and 1/33)
• Built-in 4MHz crystal oscillator and reference divider
• Programmable divider (10-bit M counter, 5-bit S counter)
• Tri-state phase comparator
• Lock detector
• Band switch driver
• Op. Amp for direct tuning
1
1 page  
MITSUBISHI ICS (TV)
M64892AFP/GP
SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR
METHOD OF SETTING DATA
The frequency demultiplying ratio uses 15bits. Setting up the band
switching output uses 4bits.
The test mode data uses 8bits. The total bits used is 27bits. Data is
read in when the enable signal is "H" and the clock signal falls.
The band switching data is read in at the 4th pulse of the clock
signal. The program counter data is read into the latch by the fall of
the enable signal after the 18th pulse of the clock signal or the fall of
the 19th pulse of the clock signal. When the enable signal goes to
"L" before the 18th pulse of the enable signal, only the band SW
data is updated and other data is ignored.
The shift register is equipped with the 18/19 bit automatic decision
function. When the 18th bit data is used, the M9 bit of the program
counter is reset and the 1/512 division of the reference frequency is
set. In case of the 19th bit, 1/1024 division of the reference
frequency is set.
(1) Transfer of the 18th bit data
Data is latched by the fall of the enable signal after the 18th clock
signal. At this time, the division of the 1/512 of the reference
frequency is used.
ENA
DATA
CLK
BS4 BS3 BS2 BS1 28 27 26 25 24 23 22 21 20 24 23 22 21 20
M8 M7 M6 M5 M4 M3 M2 M1 M0 S4 S3 S2 S1 S0
BAND SW
DATA
M COUNTER DIVISION
RATIO SETTING
READ INTO LATCH
S COUNTER DIVISION
RATIO SETTING
READ INTO LATCH
(2) Transfer of the 19th bit data
The data is latched at the 19th pulse of the clock signal. At this time,
1/1024 frequency division ratio is used. Clock signals after the
above are invalid.
Notice) To change reference frequency, set up as ENA in "L" after
19th pulse of clock signal by all means
ENA
DATA
CLK
BS4 BS3 BS2 BS1 29 28 27 26 25 24 23 22 21 20 24 23 22 21 20
M9 M8 M7 M6 M5 M4 M3 M2 M1 M0 S4 S3 S2 S1 S0
BAND SW
DATA
M COUNTER DIVISION
RATIO SETTING
READ INTO LATCH
S COUNTER DIVISION
RATIO SETTING
READ INTO LATCH
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet M64892GP.PDF ] | |
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