M5M5V5636GP16 Datasheet PDF - Mitsubishi
| Part Number | M5M5V5636GP16 | |
| Description | 18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM | |
| Manufacturers | Mitsubishi | |
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2001.July Rev.0.1
Advanced Information
Notice: This is not final specification.
Some parametric limits are subject to change.
DESCRIPTION
The M5M5V5636GP is a family of 18M bit synchronous SRAMs
organized as 524288-words by 36-bit. It is designed to eliminate
dead bus cycles when turning the bus around between reads and
writes, or writes and reads. Mitsubishi's SRAMs are fabricated
with high performance, low power CMOS technology, providing
greater reliability. M5M5V5636GP operates on 3.3V power/ 2.5V
I/O supply or a single 3.3V power supply and are 3.3V CMOS
compatible.
FEATURES
• Fully registered inputs and outputs for pipelined operation
• Fast clock speed: 167 MHz
• Fast access time: 3.8 ns
• Single 3.3V -5% and +5% power supply VDD
• Separate VDDQ for 3.3V or 2.5V I/O
• Individual byte write (BWa# - BWd#) controls may be tied
LOW
• Single Read/Write control pin (W#)
• CKE# pin to enable clock and suspend operations
• Internally self-timed, registers outputs eliminate the need to
control G#
• Snooze mode (ZZ) for power down
• Linear or Interleaved Burst Modes
• Three chip enables for simple depth expansion
MITSUBISHI LSIs
M5M5V5636GP –16
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
APPLICATION
High-end networking products that require high bandwidth, such
as switches and routers.
FUNCTION
Synchronous circuitry allows for precise cycle control
triggered by a positive edge clock transition.
Synchronous signals include : all Addresses, all Data Inputs, all
Chip Enables (E1#, E2, E3#), Address Advance/Load (ADV),
Clock Enable (CKE#), Byte Write Enables (BWa#, BWb#, BWc#,
BWd#) and Read/Write (W#). Write operations are controlled by
the four Byte Write Enables (BWa# - BWd#) and Read/Write(W#)
inputs. All writes are conducted with on-chip synchronous self-
timed write circuitry.
Asynchronous inputs include Output Enable (G#), Clock (CLK)
and Snooze Enable (ZZ). The HIGH input of ZZ pin puts the
SRAM in the power-down state.The Linear Burst order (LBO#) is
DC operated pin. LBO# pin will allow the choice of either an
interleaved burst, or a linear burst.
All read, write and deselect cycles are initiated by the ADV
LOW input. Subsequent burst address can be internally
generated as controlled by the ADV HIGH input.
Package
100pin TQFP
PART NAME TABLE
Part Name
Frequency
M5M5V5636GP - 16 167MHz
Access
3.8ns
Cycle
6.0ns
Active Current
(max.)
340mA
Standby Current
(max.)
20mA
1
MITSUBISHI
Advanced Information
ELECTRIC
M5M5V5636GP REV.0.1
|
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MITSUBISHI LSIs
M5M5V5636GP –16
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
DC OPERATED TRUTH TABLE
Name
Input Status
Operation
LBO#
HIGH or NC
LOW
Interleaved Burst Sequence
Linear Burst Sequence
Note4. LBO# is DC operated pin.
Note5. NC means No Connection.
Note6. See BURST SEQUENCE TABLE about interleaved and Linear Burst Sequence.
BURST SEQUENCE TABLE
Interleaved Burst Sequence (when LBO# = HIGH or NC)
Operation
A18~A2
First access, latch external address
A18~A2
Second access(first burst address)
latched A18~A2
Third access(second burst address)
latched A18~A2
Fourth access(third burst address)
latched A18~A2
A1,A0
0,0 0,1 1,0 1,1
0,1 0,0 1,1 1,0
1,0 1,1 0,0 0,1
1,1 1,0 0,1 0,0
Linear Burst Sequence (when LBO# = LOW)
Operation
A18~A2
First access, latch external address
A18~A2
Second access(first burst address)
latched A18~A2
Third access(second burst address)
latched A18~A2
Fourth access(third burst address)
latched A18~A2
Note7. The burst sequence wraps around to its initial state upon completion.
A1,A0
0,0 0,1 1,0 1,1
0,1 1,0 1,1 0,0
1,0 1,1 0,0 0,1
1,1 0,0 0,1 1,0
TRUTH TABLE
Address
E1# E2 E3# ZZ
ADV W# BWx#
G# CKE# CLK
DQ
used
Operation
H X X L L X X X L L->H High-Z None Deselect Cycle
X L X L L X X X L L->H High-Z None Deselect Cycle
X X H L L X X X L L->H High-Z None Deselect Cycle
X X X L H X X X L L->H High-Z None Continue Deselect Cycle
L H L L L H X L L L->H Q External Read Cycle, Begin Burst
X X X L H X X L L L->H Q Next Read Cycle, Continue Burst
L H L L L H X H L L->H High-Z External NOP/Dummy Read, Begin Burst
X X X L H X X H L L->H High-Z Next Dummy Read, Continue Burst
L H L L L L L X L L->H D External Write Cycle, Begin Burst
X X X L H X L X L L->H D Next Write Cycle, Continue Burst
L H L L L L H X L L->H High-Z None NOP/Write Abort, Begin Burst
X X X L H X H X L L->H High-Z Next Write Abort, Continue Burst
XX X L X X
X
X
H L->H
-
Current Ignore Clock edge, Stall
X X X H X X X X X X High-Z None Snooze Mode
Note8. X means "don't care". H means logic HIGH. L means logic LOW.
Note9. BWx#=H means all Synchronous Byte Write Enables (BWa#,BWb#,BWc#,BWd#) are HIGH. BWx#=L means one or more
Synchronous Byte Write Enables are LOW.
Note10. All inputs except G# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5
MITSUBISHI
Advanced Information
ELECTRIC
M5M5V5636GP REV.0.1
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