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PDF M5M54R08AJ-12 Data sheet ( Hoja de datos )
| Número de pieza | M5M54R08AJ-12 | |
| Descripción | 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM | |
| Fabricantes | Mitsubishi | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de M5M54R08AJ-12 (archivo pdf) en la parte inferior de esta página. Total 6 Páginas | ||
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1998.11.30 Ver..B
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
MITSUBISHI LSIs
M5M54R08AJ-10,-12,-15
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
DESCRIPTION
The M5M54R08AJ is a family of 524288-word by 8-bit
static RAMs, fabricated with the high performance CMOS
silicon gate process and designed for high speed
application.
These devices operate on a single 3.3V supply, and are
directly TTL compatible. They include a power down
feature as well.
FEATURES
•Fast access time
M5M54R08AJ-10 ... 10ns(max)
M5M54R08AJ-12 ... 12ns(max)
M5M54R08AJ-15 ... 15ns(max)
•Single +3.3V power supply
•Fully static operation : No clocks, No refresh
•Common data I/O
•Easy memory expansion by S
•Three-state outputs : OR-tie capability
•OE prevents data contention in the I/O bus
•Directly TTL compatible : All inputs and outputs
PIN CONFIGURATION (TOP VIEW)
A0 1
address
inputs
A1 2
A2 3
A3 4
chip select
input
data inputs/
outputs
A4
S
DQ1
DQ2
5
6
7
8
(3.3V) VCC 9
(0V) GND 10
data
inputs/
DQ3 11
outputs DQ4 12
write control
input
W 13
A5 14
address
inputs
A6 15
A7 16
A8 17
A9 18
36 NC
35 A18
34 A17
33 A16
address
inputs
32 A15 output enable
31 OE input
30 DQ8
29 DQ7
data
inputs/
outputs
28 GND (0V)
27 VCC (3.3V)
26 DQ6
25 DQ5
data
inputs/
outputs
24 A14
23 A13
22 A12
21 A11
20 A10
address
inputs
19 NC
Outline 36P0K (SOJ)
APPLICATION
High-speed memory units
BLOCK DIAGRAM
A0 1
A1 2
A2 3
A3 4
address
inputs A4 5
A5 14
A6 15
A7 16
A8 17
A9 18
S6
W 13
OE 31
PACKAGE
M5M54R08AJ
: 36pin 400mil SOJ
MEMORY ARRAY
1024 ROWS
4096 COLUMNS
COLUMN I/O CIRCUITS
CCOOLLUUMMNNADDRESS
ADDDREECSOSDERS
DECODERS
COLUMN INPUT BUFFERS
7 DQ1
8 DQ2
11 DQ3
12 DQ4
25 DQ5
26 DQ6
29 DQ7
30 DQ8
data
inputs/
outputs
9 VCC (3.3V)
27
10
GND(0V)
28
20 21 22 23 24 32 33 34 35
A10 A11 A12 A13 A14 A15 A16 A16 A17
address inputs
MITSUBISHI
ELECTRIC
1
1 page  
MITSUBISHI LSIs
M5M54R08AJ-10,-12,-15
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
(4)TIMING DIAGRAMS
Read cycle 1
A 0~18
VIH
VIL
DQ1~8 VOH
VOL
tv(A)
PREVIOUS DATA VALID
W=H
S=L
OE=L
t CR
ta(A)
UNKNOWN
tv(A)
DATA VALID
Read cycle 2 (Note 3)
VIH
S VIL
t CR
ta(S)
(Note 4)
ten(S)
(Note 4)
tdis(S)
DQ1~8
VOH
VOL
ICC1
Icc
ICC2
UNKNOWN
tPU
50%
DATA VALID
tPD
50%
W=H
OE=L
Note 3. Addresses valid prior to or coincident with S transition low.
4. Transition is measured ±500mv from steady state voltage with specified loading in Figure 2.
Read cycle 3 (Note 5)
VIH
OE VIL
t CR
ta(OE)
(Note 4)
tdis(OE)
(Note 4) ten(OE)
DQ1~8
VOH
VOL
W=H
S=L
UNKNOWN
DATA VALID
Note 5. Addresses and S valid prior to OE transition low by (ta(A)-ta(OE)), (ta(S)-ta(OE))
MITSUBISHI
ELECTRIC
5
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet M5M54R08AJ-12.PDF ] | |
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