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PDF M5M4V64S40ATP-10L Data sheet ( Hoja de datos )
| Número de pieza | M5M4V64S40ATP-10L | |
| Descripción | 64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM | |
| Fabricantes | Mitsubishi | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de M5M4V64S40ATP-10L (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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SDRAM (Rev.1.3)
Mar'98
MITSUBISHI LSIs
M5M4V64S40ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
Some of contents are subject to change without notice.
DESCRIPTION
PIN CONFIGURATION
(TOP VIEW)
The M5M4V64S40ATP is a 4-bank x 1048576-word x 16-bit
Synchronous DRAM, with LVTTL interface. All inputs and
outputs are referenced to the rising edge of CLK. The
Vdd
DQ0
VddQ
DQ1
1
2
3
4
54 Vss
53 DQ15
52 VssQ
51 DQ14
M5M4V64S40ATP achieves very high speed data rate up to
125MHz, and is suitable for main memory or graphic memory
in computer systems.
DQ2
VssQ
DQ3
DQ4
VddQ
DQ5
5
6
7
8
9
10
50 DQ13
49 VddQ
48 DQ12
47 DQ11
46 VssQ
45 DQ10
FEATURES
- Single 3.3v±0.3v power supply
- Clock frequency 125MHz /100MHz
DQ6
VssQ
DQ7
Vdd
DQML
/WE
11
12
13
14
15
16
44 DQ9
43 VddQ
42 DQ8
41 Vss
40 NC (Vref)
39 DQMU
- Fully synchronous operation referenced to clock rising edge
- 4 bank operation controlled by BA0, BA1 (Bank Address)
- /CAS latency- 2/3 (programmable)
- Burst length- 1/2/4/8/Full Page (programmable)
/CAS
/RAS
/CS
BA0(A13)
BA1(A12)
A10
A0
17
18
19
20
21
22
23
38 CLK
37 CKE
36 NC
35 A11
34 A9
33 A8
32 A7
- Burst type- sequential / interleave (programmable)
- Column access - random
- Burst Write / Single Write (programmable)
A1 24
A2 25
A3 26
Vdd 27
31 A6
30 A5
29 A4
28 Vss
- Auto precharge / All bank precharge controlled by A10
- Auto refresh and Self refresh
- 4096 refresh cycles /64ms
- Column address A0-A7
CLK
CKE
/CS
/RAS
: Master Clock
: Clock Enable
: Chip Select
: Row Address Strobe
- LVTTL Interface
- 400-mil, 54-pin Thin Small Outline Package (TSOP II) with
0.8mm lead pitch
/CAS
/WE
DQ0-15
DQML/U
: Column Address Strobe
: Write Enable
: Data I/O
: Output Disable/ Write Mask
Max.
Frequency
CLK Access
Time
A0-11
BA0,1
Vdd
: Address Input
: Bank Address
: Power Supply
M5M4V64S40ATP-8A
M5M4V64S40ATP-8
125MHz
100MHz
6ns
6ns
VddQ
Vss
VssQ
: Power Supply for Output
: Ground
: Ground for Output
M5M4V64S40ATP-10
100MHz
8ns
MITSUBISHI ELECTRIC
1
1 page  
SDRAM (Rev.1.3)
Mar'98
MITSUBISHI LSIs
M5M4V64S40ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
COMMAND TRUTH TABLE
COMMAND
MNEMONIC
Deselect
No Operation
Row Address Entry &
Bank Activate
Single Bank Precharge
Precharge All Banks
Column Address Entry
& Write
Column Address Entry
& Write with Auto-
Precharge
Column Address Entry
& Read
Column Address Entry
& Read with Auto-
Precharge
Auto-Refresh
Self-Refresh Entry
DESEL
NOP
ACT
PRE
PREA
WRITE
WRITEA
READ
READA
REFA
REFS
Self-Refresh Exit
REFSX
Burst Terminate
Mode Register Set
TBST
MRS
CKE
n-1
H
H
H
H
H
H
H
H
H
H
H
L
L
H
H
CKE
n
X
X
X
X
X
X
X
X
X
H
L
H
H
X
X
/CS /RAS /CAS /WE BA0,1 A11
HX XXXX
LHHHXX
L L HHVV
L L HLVX
L L H L XX
LHL LVX
LHL LVX
LHL HVX
LHL HVX
L L L HXX
L L L HXX
HX XXXX
LHHHXX
L HH LXX
LLLLLL
A10 A0-9
XX
XX
VV
LX
HX
LV
HV
LV
HV
XX
XX
XX
XX
XX
L V*1
H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number
NOTE:
1. A7-A9 =0, A0-A6 =Mode Address
MITSUBISHI ELECTRIC
5
5 Page 
SDRAM (Rev.1.3)
Mar'98
MITSUBISHI LSIs
M5M4V64S40ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
SIMPLIFIED STATE DIAGRAM
SELF
REFRESH
REFS
REFSX
MODE
REGISTER
SET
MRS
IDLE
REFA
AUTO
REFRESH
CKEL
CLK
SUSPEND
CKEH
ACT
CKEL
POWER
DOWN
CKEH
TBST (for Full Page)
WRITE
ROW
ACTIVE
TBST (for Full Page)
READ
CKEL
WRITE
SUSPEND
WRITE
CKEH
WRITEA READA
READ
WRITE
READ
CKEL
READ
SUSPEND
CKEH
WRITEA
CKEL
WRITEA
SUSPEND
WRITEA
CKEH
WRITEA
READA
PRE
PRE
PRE
READA
CKEL
READA
READA
SUSPEND
CKEH
POWER
APPLIED
POWER
ON
PRE
PRE
CHARGE
MITSUBISHI ELECTRIC
Automatic Sequence
Command Sequence
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet M5M4V64S40ATP-10L.PDF ] | |
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