M5M4V64S30ATP-8L Datasheet PDF - Mitsubishi
| Part Number | M5M4V64S30ATP-8L | |
| Description | 64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM | |
| Manufacturers | Mitsubishi | |
| Logo |  |
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SDRAM (Rev.1.3)
Mar'98
MITSUBISHI LSIs
M5M4V64S30ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
Some of contents are subject to change without notice.
DESCRIPTION
PIN CONFIGURATION
(TOP VIEW)
The M5M4V64S30ATP is a 4-bank x 2097152-word x 8-bit
Synchronous DRAM, with LVTTL interface. All inputs and
outputs are referenced to the rising edge of CLK. The
Vdd
DQ0
VddQ
NC
1
2
3
4
54 Vss
53 DQ7
52 VssQ
51 NC
M5M4V64S30ATP achieves very high speed data rate up to
125MHz, and is suitable for main memory or graphic memory
in computer systems.
DQ1
VssQ
NC
DQ2
VddQ
NC
5
6
7
8
9
10
50 DQ6
49 VddQ
48 NC
47 DQ5
46 VssQ
45 NC
FEATURES
DQ3
VssQ
NC
11
12
13
44 DQ4
43 VddQ
42 NC
- Single 3.3v±0.3v power supply
- Clock frequency 125MHz /100MHz
Vdd 14
NC 15
/WE 16
41 Vss
40 NC
39 DQM
- Fully synchronous operation referenced to clock rising edge
/CAS
/RAS
- 4 bank operation controlled by BA0, BA1 (Bank Address)
/CS
BA0(A13)
- /CAS latency- 2/3 (programmable)
BA1(A12)
- Burst length- 1/2/4/8/Full Page (programmable)
A10
A0
- Burst type- sequential / interleave (programmable)
A1
A2
- Column access - random
A3
- Burst Write / Single Write (programmable)
Vdd
17
18
19
20
21
22
23
24
25
26
27
38 CLK
37 CKE
36 NC
35 A11
34 A9
33 A8
32 A7
31 A6
30 A5
29 A4
28 Vss
- Auto precharge / All bank precharge controlled by A10
- Auto refresh and Self refresh
- 4096 refresh cycles /64ms
- Column address A0-A8
CLK
CKE
/CS
/RAS
: Master Clock
: Clock Enable
: Chip Select
: Row Address Strobe
- LVTTL Interface
- 400-mil, 54-pin Thin Small Outline Package (TSOP II) with
0.8mm lead pitch
/CAS
/WE
DQ0-7
DQM
: Column Address Strobe
: Write Enable
: Data I/O
: Output Disable/ Write Mask
Max.
Frequency
CLK Access
Time
A0-11
BA0,1
Vdd
: Address Input
: Bank Address
: Power Supply
M5M4V64S30ATP-8A
125MHz
6ns
VddQ
: Power Supply for Output
M5M4V64S30ATP-8
100MHz
6ns
Vss
VssQ
: Ground
: Ground for Output
M5M4V64S30ATP-10
100MHz
8ns
MITSUBISHI ELECTRIC
1
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SDRAM (Rev.1.3)
Mar'98
MITSUBISHI LSIs
M5M4V64S30ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
COMMAND TRUTH TABLE
COMMAND
MNEMONIC
Deselect
No Operation
Row Address Entry &
Bank Activate
Single Bank Precharge
Precharge All Banks
Column Address Entry
& Write
Column Address Entry
& Write with Auto-
Precharge
Column Address Entry
& Read
Column Address Entry
& Read with Auto-
Precharge
Auto-Refresh
Self-Refresh Entry
DESEL
NOP
ACT
PRE
PREA
WRITE
WRITEA
READ
READA
REFA
REFS
Self-Refresh Exit
REFSX
Burst Terminate
Mode Register Set
TBST
MRS
CKE
n-1
H
H
H
H
H
H
H
H
H
H
H
L
L
H
H
CKE
n
X
X
X
X
X
X
X
X
X
H
L
H
H
X
X
/CS /RAS /CAS /WE BA0,1 A11
HX XXXX
LHHHXX
L L HHVV
L L HLVX
L L H L XX
LHL LVX
LHL LVX
LHL HVX
LHL HVX
L L L HXX
L L L HXX
HX XXXX
LHHHXX
L HH LXX
LLLLLL
A10 A0-9
XX
XX
VV
LX
HX
LV
HV
LV
HV
XX
XX
XX
XX
XX
L V*1
H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number
NOTE:
1. A7-A9 =0, A0-A6 =Mode Address
MITSUBISHI ELECTRIC
5
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for M5M4V64S30ATP-8L electronic component. |
| Information | Total 30 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ M5M4V64S30ATP-8L.PDF Datasheet ] | |
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Featured Datasheets
| Part Number | Description | MFRS |
| M5M4V64S30ATP-8 | The function is 64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM. Mitsubishi | |
| M5M4V64S30ATP-8A | The function is 64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM. Mitsubishi | |
| M5M4V64S30ATP-8L | The function is 64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM. Mitsubishi | |
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