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Numéro de référence | M5M4V4S40CTP-15 | ||
Description | 4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM | ||
Fabricant | Mitsubishi | ||
Logo | |||
SDRAM (Rev. 0.3)
Feb ‘97 Preliminary
MITSUBISHI LSIs
M5M4V4S40CTP-12, -15
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
PRELIMINARY
Some of contents are described for general products
and are subject to change without notice.
DESCRIPTION
PIN CONFIGURATION
The M5M4V4S40CTP is a 2-bank x 131,072-word x 16-bit
(TOP VIEW)
Synchronous DRAM, with LVTTL interface. All inputs and Vdd
outputs are referenced to the rising edge of CLK. The
DQ0
1
2
50 Vss
49 DQ15
M5M4V4S40CTP achieves very high speed data rates up to DQ1
83MHz, and is suitable for main memory or graphic memory
VssQ
DQ2
in computer systems.
DQ3
3
4
5
6
48 DQ14
47 VssQ
46 DQ13
45 DQ12
VddQ 7
44 VddQ
DQ4
8
43 DQ11
FEATURES
DQ5
VssQ
DQ6
9
10
11
42 DQ10
41 VssQ
40 DQ9
- Single 3.3v±0.3v power supply
- Clock frequency 83MHz / 67MHz
DQ7
VddQ
DQML
12
13
14
39 DQ8
38 VddQ
37 NC
- Fully synchronous operation referenced to clock rising edge /WE 15
- Dual bank operation controlled by BA(Bank Address)
- /CAS latency- 1/2/3 (programmable)
/CAS
/RAS
/CS
16
17
18
- Burst length- 1/2/4/8/FP (programmable)
BA 19
36 DQMU
35 CLK
34 CKE
33 NC
32 NC
- Sequential and interleave burst (programmable)
- Byte control by DQMU and DQML
- Random column access
- Auto precharge / All bank precharge controlled by A8
- Auto and self refresh
A8 20
A0 21
A1 22
A2 23
A3 24
Vdd 25
31 NC
30 A7
29 A6
28 A5
27 A4
26 Vss
- 1024 refresh cycles /16.4ms
- LVTTL Interface
- 400-mil, 50-pin Thin Small Outline Package
(TSOP II) with 0.8mm lead pitch
CLK
CKE
/CS
/RAS
: Master Clock
: Clock Enable
: Chip Select
: Row Address Strobe
/CAS
: Column Address Strobe
/WE : Write Enable
DQ0-15
: Data I/O
DQMU
: Upper Output Disable/ Write Mask
DQML
: Lower Output Disable/ Write Mask
A0-8
: Address Input
BA : Bank Address
Max.
CLK Access
Frequency
Time
Vdd
VddQ
Vss
: Power Supply
: Power Supply for Output
: Ground
M5M4V4S40CTP-12
83MHz
8ns
VssQ
: Ground for Output
M5M4V4S40CTP-15
67MHz
9ns
MITSUBISHI ELECTRIC
1
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Pages | Pages 30 | ||
Télécharger | [ M5M4V4S40CTP-15 ] |
No | Description détaillée | Fabricant |
M5M4V4S40CTP-12 | 4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM | Mitsubishi |
M5M4V4S40CTP-15 | 4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM | Mitsubishi |
US18650VTC5A | Lithium-Ion Battery | Sony |
TSPC106 | PCI Bus Bridge Memory Controller | ATMEL |
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