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PDF M59MR032C Data sheet ( Hoja de datos )
| Número de pieza | M59MR032C | |
| Descripción | 32 Mbit 2Mb x16 / Mux I/O / Dual Bank / Burst 1.8V Supply Flash Memory | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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M59MR032C
M59MR032D
32 Mbit (2Mb x16, Mux I/O, Dual Bank, Burst)
1.8V Supply Flash Memory
s SUPPLY VOLTAGE
– VDD = VDDQ = 1.65V to 2.0V for Program,
Erase and Read
– VPP = 12V for fast Program (optional)
s MULTIPLEXED ADDRESS/DATA
s SYNCHRONOUS / ASYNCHRONOUS READ
– Configurable Burst mode Read
– Page mode Read (4 Words Page)
– Random Access: 100ns
s PROGRAMMING TIME
– 10µs by Word typical
– Double Word Programming Option
s MEMORY BLOCKS
– Dual Bank Memory Array: 8 Mbit - 24 Mbit
– Parameter Blocks (Top or Bottom location)
s DUAL BANK OPERATIONS
– Read within one Bank while Program or
Erase within the other
– No delay between Read and Write operations
s BLOCK PROTECTION/UNPROTECTION
– All Blocks protected at Power-up
– Any combination of Blocks can be protected
s COMMON FLASH INTERFACE (CFI)
s 64 bit SECURITY CODE
s ERASE SUSPEND and RESUME MODES
s 100,000 PROGRAM/ERASE CYCLES per
BLOCK
s ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Top Device Code, M59MR032C: A4h
– Bottom Device Code, M59MR032D: A5h
BGA µBGA
LFBGA54 (ZC)
10 x 4 ball array
µBGA46 (GC)
10 x 4 ball array
Figure 1. Logic Diagram
VDD VDDQ VPP
5
A16-A20
16
ADQ0-ADQ15
W
E WAIT
G M59MR032C
M59MR032D
RP BINV
WP
L
K
VSS
AI90109
April 2001
1/49
1 page  
M59MR032C, M59MR032D
Organization
The M59MR032 is organized as 2Mbit by 16 bits.
The first sixteen address lines are multiplexed with
the Data Input/Output signals on the multiplexed
address/data bus ADQ0-ADQ15. The remaining
address lines A16-A20 are the MSB addresses.
Memory control is provided by Chip Enable E, Out-
put Enable G and Write Enable W inputs.
The clock K input synchronizes the memory to the
microprocessor during burst read.
Reset RP is used to reset all the memory circuitry
and to set the chip in power-down mode if this
function is enabled by a proper setting of the Con-
figuration Register. Erase and Program operations
are controlled by an internal Program/Erase Con-
troller (P/E.C.). Status Register data output on
ADQ7 provides a Data Polling signal, ADQ6 and
ADQ2 provide Toggle signals and ADQ5 provides
error bit to indicate the state of the P/E.C opera-
tions. WAIT output indicates to the microprocessor
the status of the memory during the burst mode
operations.
Memory Blocks
The device features asymmetrically blocked archi-
tecture. M59MR032 has an array of 71 blocks and
is divided into two banks A and B, providing Dual
Bank operations. While programming or erasing in
Bank A, read operations are possible into Bank B
or vice versa. The memory also features an erase
suspend allowing to read or program in another
block within the same bank. Once suspended the
erase can be resumed. The Bank Size and Sector-
ization are summarized in Table 8. Parameter
Blocks are located at the top of the memory ad-
dress space for the M59MR032C, and at the bot-
tom for the M59MR032D. The memory maps are
shown in Tables 4, 5, 6 and 7.
The Program and Erase operations are managed
automatically by the P/E.C. Block protection
against Program or Erase provides additional data
security. Instructions are provided to protect or un-
protect any block in the application. A second reg-
ister locks the protection status while WP is low
(see Block Locking description). All blocks are pro-
tected and unlocked at Power-up.
Table 3. Bank Size and Sectorization
Bank Size
Bank A
8 Mbit
Bank B
24 Mbit
Parameter Blocks
8 blocks of 4 KWord
-
Main Blocks
15 blocks of 32 KWord
48 blocks of 32 KWord
5/49
5 Page 
M59MR032C, M59MR032D
Figure 4. Read Operation Sequence when CR15 = 0 (excluding Read Memory Array)
K
L
A16-A20
ADQ0-ADQ15
ADQ0-ADQ15
ADQ0-ADQ15
VALID ADDRESS
CONF. CODE 2
VALID ADDRESS
VALID DATA NOT VALID
CONFIGURATION CODE 3
VALID ADDRESS
VALID DATA
CONFIGURATION CODE 6
VALID ADDRESS
NOT VALID
NOT VALID
VALID DATA
AI90112
Burst Read. The device also supports a burst
read. In this mode, an address is first latched on
the rising edge of L or K (or falling edge of K, ac-
cording to configuration settings); after a config-
urable delay of 2 to 6 clock cycles a new data is
output at each clock cycle. The burst sequence
may be configured for linear or interleaved order
and for a length of 4, 8 words or for continuous
burst mode.
A WAIT signal may be asserted to indicate to the
system that an output delay will occur.
This delay will depend on the starting address of
the burst sequence; the worst case delay will oc-
cur when the sequence is crossing a 32 word
boundary and the starting address was at the end
of a four word boundary. See the Write Configura-
tion Register (CR) Instruction for more details on
all the possible settings for the synchronous burst
read.
Write. Write operations are used to give Instruc-
tion Commands to the memory or to latch Input
Data to be programmed. A write operation is initi-
ated when Chip Enable E and Write Enable W are
at VIL with Output Enable G at VIH. Addresses are
latched on the rising edge of L. Commands and In-
put Data are latched on the rising edge of W or E
whichever occurs first. Noise pulses of less than
5ns typical on E, W and G signals do not start a
write cycle. Write operations are asynchronous
and clock is ignored during write.
Dual Bank Operations. The Dual Bank allows to
read data from one bank of memory while a pro-
gram or erase operation is in progress in the other
bank of the memory. Read and Write cycles can
be initiated for simultaneous operations in different
banks without any delay. Status Register during
Program or Erase must be monitored using an ad-
dress within the bank being modified.
Output Disable. The data outputs are high im-
pedance when the Output Enable G is at VIH with
Write Enable W at VIH.
Standby. The memory is in standby when Chip
Enable E is at VIH and the P/E.C. is idle. The pow-
er consumption is reduced to the standby level
and the outputs are high impedance, independent
of the Output Enable G or Write Enable W inputs.
Automatic Standby. When in Read mode, after
150ns of bus inactivity and when CMOS levels are
driving the addresses, the chip automatically en-
ters a pseudo-standby mode where consumption
is reduced to the CMOS standby value, while out-
puts still drive the bus. The automatic standby fea-
ture is not available when the device is configured
for synchronous burst mode.
Power-down. The memory is in Power-down
when the Configuration Register is set for Power-
down and RP is at VIL. The power consumption is
reduced to the Power-down level, and Outputs are
in high impedance, independent of the Chip En-
able E, Output Enable G or Write Enable W inputs.
Block Locking. Any combination of blocks can
be temporarily protected against Program or
Erase by setting the lock register and pulling WP
to VIL (see Block Lock instruction).
11/49
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| PDF Descargar | [ Datasheet M59MR032C.PDF ] | |
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