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PDF M59DR032B Data sheet ( Hoja de datos )
| Número de pieza | M59DR032B | |
| Descripción | 32 Mbit 2Mb x16 / Dual Bank / Page Low Voltage Flash Memory | |
| Fabricantes | ST Microelectronics | |
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M59DR032A
M59DR032B
32 Mbit (2Mb x16, Dual Bank, Page) Low Voltage Flash Memory
PRELIMINARY DATA
s SUPPLY VOLTAGE
– VDD = VDDQ = 1.65V to 2.2V: for Program,
Erase and Read
– VPP = 12V: optional Supply Voltage for fast
Program and Erase
s ASYNCHRONOUS PAGE MODE READ
– Page Width: 4 words
– Page Access: 35ns
– Random Access: 100ns
s PROGRAMMING TIME
– 10µs by Word typical
– Double Word Programming Option
s MEMORY BLOCKS
– Dual Bank Memory Array: 4 Mbit - 28 Mbit
– Parameter Blocks (Top or Bottom location)
– Main Blocks
s DUAL BANK OPERATIONS
– Read within one Bank while Program or
Erase within the other
– No delay between Read and Write operations
s BLOCK PROTECTION/UNPROTECTION
– All Blocks protected at Power Up
– Any combination of Blocks can be protected
– WP for Block Locking
s COMMON FLASH INTERFACE (CFI)
s 64 bit SECURITY CODE
s ERASE SUSPEND and RESUME MODES
s 100,000 PROGRAM/ERASE CYCLES per
BLOCK
s 20 YEARS DATA RETENTION
– Defectivity below 1ppm/year
s ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code, M59DR032A: A0h
– Device Code, M59DR032B: A1h
TSOP48 (N)
12 x 20mm
BGA
FBGA48 (ZB)
8 x 6 solder balls
Figure 1. Logic Diagram
VDD VDDQ VPP
21
A0-A20
16
DQ0-DQ15
W
E M59DR032A
G M59DR032B
RP
WP
VSS
AI02544B
October 1999
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1/38
1 page  
Table 5. Bank B, Bottom Boot Block Address
Size (KWord)
Address Range
32 1F8000h-1FFFFFh
32 1F0000h-1F7FFFh
32 1E8000h-1EFFFFh
32 1E0000h-1E7FFFh
32 1D8000h-1DFFFFh
32 1D0000h-1D7FFFh
32 1C8000h-1CFFFFh
32 1C0000h-1C7FFFh
32 1B8000h-1BFFFFh
32 1B0000h-1B7FFFh
32 1A8000h-1AFFFFh
32 1A0000h-1A7FFFh
32 198000h-19FFFFh
32 190000h-197FFFh
32 188000h-18FFFFh
32 180000h-187FFFh
32 178000h-17FFFFh
32 170000h-177FFFh
32 168000h-16FFFFh
32 160000h-167FFFh
32 158000h-15FFFFh
32 150000h-157FFFh
32 148000h-14FFFFh
32 140000h-147FFFh
32 138000h-13FFFFh
32 130000h-137FFFh
32 128000h-12FFFFh
32 120000h-127FFFh
32 118000h-11FFFFh
32 110000h-117FFFh
32 108000h-10FFFFh
32 100000h-107FFFh
32 0F8000h-0FFFFFh
32 0F0000h-0F7FFFh
32 0E8000h-0EFFFFh
32 0E0000h-0E7FFFh
M59DR032A, M59DR032B
32 0D8000h-0DFFFFh
32 0D0000h-0D7FFFh
32 0C8000h-0CFFFFh
32 0C0000h-0C7FFFh
32 0B8000h-0BFFFFh
32 0B0000h-0B7FFFh
32 0A8000h-0AFFFFh
32 0A0000h-0A7FFFh
32 098000h-09FFFFh
32 090000h-097FFFh
32 088000h-08FFFFh
32 080000h-087FFFh
32 078000h-07FFFFh
32 070000h-077FFFh
32 068000h-06FFFFh
32 060000h-067FFFh
32 058000h-05FFFFh
32 050000h-057FFFh
32 048000h-04FFFFh
32 040000h-047FFFh
Table 6. Bank A, Bottom Boot Block Address
Size (KWord)
Address Range
32 038000h-03FFFFh
32 030000h-037FFFh
32 028000h-02FFFFh
32 020000h-027FFFh
32 018000h-01FFFFh
32 010000h-017FFFh
32 008000h-00FFFFh
4 007000h-007FFFh
4 006000h-006FFFh
4 005000h-005FFFh
4 004000h-004FFFh
4 003000h-003FFFh
4 002000h-002FFFh
4 001000h-001FFFh
4 000000h-000FFFh
5/38
5 Page 
M59DR032A, M59DR032B
Bank Erase (BKE) Instruction. This instruction
uses six write cycles and is used to erase all the
blocks belonging to the selected bank. The Erase
Set-up command 80h is written to address 555h
on the third cycle after the two Coded cycles. The
Bank Erase Confirm command 10h is similarly
written on the sixth cycle after another two Coded
cycles at an address within the selected bank. If
the second command given is not an erase con-
firm or if the Coded cycles are wrong, the instruc-
tion aborts and the device is reset to Read Array.
It is not necessary to program the array with 00h
first as the P/E.C. will automatically do this before
erasing it to FFh. Read operations within the same
bank after the sixth rising edge of W or E output
the Status Register bits. During the execution of
the erase by the P/E.C., Data Polling bit DQ7 re-
turns ’0’, then ’1’ on completion. The Toggle bit
DQ6 toggles during erase operation and stops
when erase is completed. After completion the
Status Register bit DQ5 returns ’1’ if there has
been an Erase Failure.
Erase Suspend (ES) Instruction. In a dual bank
memory the Erase Suspend instruction is used to
read data within the bank where erase is in
progress. It is also possible to program data in
blocks not being erased.
The Erase Suspend instruction consists of writing
the command B0h without any specific address.
No Coded Cycles are required. Erase suspend is
accepted only during the Block Erase instruction
execution. The Toggle bit DQ6 stops toggling
when the P/E.C. is suspended within 15µs after
the Erase Suspend (ES) command has been writ-
ten. The device will then automatically be set to
Read Memory Array mode. When erase is sus-
pended, a Read from blocks being erased will out-
put DQ2 toggling and DQ6 at '1'. A Read from a
block not being erased returns valid data. During
suspension the memory will respond only to the
Erase Resume ER and the Program PG instruc-
tions. A Program operation can be initiated during
erase suspend in one of the blocks not being
erased. It will result in DQ6 toggling when the data
is being programmed.
Erase Resume (ER) Instruction. If an Erase
Suspend instruction was previously executed, the
erase operation may be resumed by giving the
command 30h, at an address within the bank be-
ing erased and without any Coded Cycle.
11/38
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